Circuit Arrangement

A method comprising:

• forming a first diode arrangement including at least one first diode and at least one second diode connected in anti-series between a first circuit node and a second circuit node of the first diode arrangement;
• forming a second diode arrangement including at least one first diode and at least one second diode connected in anti-series between a first circuit node and a second circuit node of the second diode arrangement;
• connecting the second circuit node of the first diode arrangement and the second circuit node of the second diode arrangement;
• and,
• connecting the first diode arrangement and the second diode arrangement in series between an input node and one of a further input node, a ground node, or a doped contact region of a semiconductor body of an electronic circuit,
• wherein forming the first diode arrangement comprises implanting first type dopant atoms into a first polysilicon layer in a first implantation process using a first implantation mask to form first implanted regions, and implanting second type dopant atoms into the first polysilicon layer in a second implantation process and using a second implantation mask to form at least one second implanted region, wherein the first implanted regions and the at least one second region are arranged alternatingly in a first direction and are separated from one another by third regions of the first polysilicon layer,
• wherein forming the second diode arrangement comprises implanting first type dopant atoms into a second polysilicon layer different from the first polysilicon layer in the first implantation process using the first implantation mask to form first implanted regions, and implanting second type dopant atoms into the second polysilicon layer in the second implantation process and using the second implantation mask to form at least one second implanted region, wherein the first implanted regions and the at least one second region are arranged alternatingly in the first direction and are separated by third regions of the second polysilicon layer, and
• wherein in each of the first and second diode arrangements, the respective second circuit node is spaced apart from the respective first circuit node in the first direction.