Display panel and display device

A display panel, comprising:

• a base substrate;
• and
• a third transistor and a fourth transistor, wherein the third transistor comprises a third active layer, a third gate, a fifth gate, a third source, and a third drain;
• the third gate and the fifth gate are located on two sides of the third active layer, respectively, and the third active layer comprises an oxide semiconductor;
• the fourth transistor comprises a fourth active layer, a sixth gate, a seventh gate, a fourth source, and a fourth drain;
• the sixth gate and the seventh gate are located on two sides of the fourth active layer, respectively, and the fourth active layer comprises the oxide semiconductor;
• wherein a length of the third gate in a first direction is L3, a length of the fifth gate in the first direction is L5, a length of the sixth gate in the first direction is L6, a length of the seventh gate in the first direction is L7, and (L3 – L6) < (L5 – L7);
• and
• the first direction is a direction pointing from a first electrode to a second electrode.

A display panel, comprising:

• a base substrate;
• and
• a second transistor, a third transistor, and a fourth transistor;
• wherein the second transistor comprises a second active layer, a second gate, a fourth gate, a second source, and a second drain;
• the second gate is located on one side of the first active layer facing away from the base substrate, the fourth gate is disposed on one side of the second active layer facing towards the base substrate, and the second active layer comprises an oxide semiconductor;
• wherein the third transistor comprises a third active layer, a third gate, a fifth gate, a third source, and a third drain;
• the third gate is disposed on one side of the third active layer facing away from the base substrate, the fifth gate is disposed on one side of the third active layer facing towards the base substrate, and the third active layer comprises the oxide semiconductor;
• the fourth transistor comprises a fourth active layer, a sixth gate, a seventh gate, a fourth source, and a fourth drain;
• the sixth gate and the seventh gate are located on two sides of the fourth active layer, respectively, and the fourth active layer comprises the oxide semiconductor;
• wherein a length of the second channel region of the second transistor is L2, a length of the third gate in a first direction is L3, a length of the fourth gate in the first direction is L4, a length of the fifth gate in the first direction is L5, a length of the sixth gate in the first direction is L6, a length of the seventh gate in the first direction is L7;
• wherein the first direction is a direction pointing from a first electrode to a second electrode, and at least one of (L3 – L2) < (L5 – L4) or (L3 – L6) < (L5 – L7) is satisfied.