Two-dimensional electron gas charge density control

A gallium nitride (GaN) resistor comprising:

• a compound semiconductor substrate;
• a first ohmic contact region formed in the compound semiconductor substrate;
• a second ohmic contact region formed in the compound semiconductor substrate and separated from the first ohmic contact region;
• an active region extending between the first ohmic contact region and the second ohmic contact region;
• a two-dimensional electron gas (2DEG) layer formed in the compound semiconductor substrate and under the active region;
• a first isolated charge control structure disposed between the first and second ohmic contact regions and overlapping a first portion of the active region;
• and
• a second isolated charge control structure disposed between the first and second ohmic contact regions and overlapping a second portion of the active region.

A gallium nitride (GaN) device comprising:

• a compound semiconductor substrate;
• a source region formed in the compound semiconductor substrate;
• a drain region formed in the compound semiconductor substrate and separated from the source region;
• a two-dimensional electron gas (2DEG) layer formed in the compound semiconductor substrate and extending between the source region and the drain region;
• a gate region formed on the compound semiconductor substrate and positioned between the source region and the drain region;
• and
• a plurality of isolated charge control structures disposed between the gate region and the drain region, wherein each of the plurality of isolated charge control structures comprises an isolation implanted region formed through each of the respective plurality of isolated charge control structures.

A method of controlling a charge density in a two-dimensional electron gas (2DEG) layer in a gallium nitride (GaN) device, the method comprising:

• providing a compound semiconductor substrate comprising a first layer and a second layer, and further comprising a 2DEG layer formed between the first layer and the second layer;
• forming an active region;
• forming a gate region on the compound semiconductor substrate and across the active region;
• forming a source region in the compound semiconductor substrate;
• forming a drain region in the compound semiconductor substrate and separated from the source region, wherein the gate region is positioned between the source region and the drain region
• forming a plurality of isolated charge control structures disposed between the gate region and the drain region;
• and
• wherein each of the plurality of isolated charge control structures are arranged to selectively reduce charge density in the 2DEG layer under each of the plurality of isolated charge control structures.