Ferroelectric memory device

A ferroelectric memory device comprising:

• a cylindrical channel layer in a channel hole;
• a gate insulating layer on an inner wall and a bottom of the cylindrical channel layer;
• an inner gate electrode in the channel hole and on the gate insulating layer;
• a spacer on the inner gate electrode and on an inner wall of a recess hole, wherein the recess hole extends in a vertical direction from an upper surface towards the bottom of the cylindrical channel layer;
• a ferroelectric layer on a side surface and an upper surface of the spacer and on the inner gate electrode;
• a control gate electrode in the recess hole and on the ferroelectric layer opposite the inner gate electrode;
• a first source and drain layer extending around a lower portion of the cylindrical channel layer;
• and
• a second source and drain layer spaced apart from the first source and drain layer in the vertical direction and extending around an upper portion of the cylindrical channel layer,
• wherein the control gate electrode, the ferroelectric layer, and the inner gate electrode comprise a horizontal capacitor,
• wherein the inner gate electrode, the gate insulating layer, and the cylindrical channel layer comprise a vertical capacitor, and
• wherein the horizontal capacitor is electrically connected in series to the vertical capacitor.

A ferroelectric memory device comprising:

• a plurality of word lines extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction;
• a plurality of first source and bit lines below the plurality of word lines in a vertical direction, extending in the second horizontal direction, and spaced apart from each other in the first horizontal direction;
• a plurality of second source and bit lines between the plurality of word lines and the plurality of first source and bit lines in the vertical direction, extending in the second horizontal direction, and spaced apart from each other in the first horizontal direction;
• and
• a plurality of vertical channel structures in a plurality of intersection areas, respectively, wherein the plurality of intersection areas each comprise an area of overlap between the plurality of word lines, the plurality of first source and bit lines, and the plurality of second source and bit lines,
• wherein each of the plurality of vertical channel structures comprises:
• a cylindrical channel layer in a channel hole;
• a gate insulating layer on an inner wall and a bottom of the cylindrical channel layer;
• an inner gate electrode on the gate insulating layer;
• a spacer on the inner gate electrode and on an inner wall of a recess hole, wherein the recess hole extends in a vertical direction from an upper surface towards the bottom of the cylindrical channel layer;
• a ferroelectric layer on a side surface and an upper surface of the spacer and on the inner gate electrode;
• a control gate electrode in the recess hole, on the ferroelectric layer opposite the inner gate electrode, and electrically connected to a respective word line of the plurality of word lines;
• a first source and drain layer extending around a lower portion of the cylindrical channel layer and connected to a respective first source and bit line of the plurality of first source and bit lines;
• and
• a second source and drain layer spaced apart from the first source and drain layer in the vertical direction, extending around an upper portion of the cylindrical channel layer, and connected to a respective second source and bit line of the plurality of second source and bit lines.