US 2026/0089969 A1Published application

Memory system and a method for controlling memory system

AssigneeJapan Science and Technology Agency

InventorsZuocheng CAI, Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi

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Abstract

A memory system including a memory cell array and a control circuit, the memory device includes a ferroelectric layer with a thickness of 3 nm or more and 7 nm or less, when the control circuit determines a number of times of executions of a program for the memory cell reaches a predetermined number of times, the control circuit applies a first positive pulse voltage having a pulse width of a (μsec) m times to the ferroelectric layer, and applies a second negative pulse voltage having a pulse width of b (μsec) n times to the ferroelectric layer so that Equation 1 and Equation 2 hold. 0.1 μsec ≦ a × m < 250 ⁢ μsec ( Equation ⁢ 1 ) 0.1 μsec ≦ b × n < 250 ⁢ μsec . ( Equation ⁢ 2 )

Claims17

Dependent claims

A memory system comprising:

a memory cell array with memory cells including a memory device arranged in a matrix;
and
a control circuit configured to control the memory cell array,
wherein
the memory device includes:
a semiconductor layer;
a gate electrode facing the semiconductor layer;
an insulating layer provided between the semiconductor layer and the gate electrode;
and
a ferroelectric layer provided between the insulating layer and the gate electrode and containing hafnium oxide,
the semiconductor layer contains silicon,
the insulating layer is in contact with the semiconductor layer,
the ferroelectric layer is in contact with the insulating layer,
a thickness of the ferroelectric layer is greater than 3 nm and less than 7 nm,
when the control circuit determines:
whether a number of times of executions of a program operation or an erase operation on the memory cells reaches a predetermined number of times;
or
whether bit error rate is a predetermined rate or more after executions of a program or an erase process on the memory cells,
the control circuit executes a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric layer so that Equation 1 and Equation 2 hold in the case where the number of times of executions reaches the predetermined number of times or the bit error rate is the predetermined rate or more,
wherein
the first voltage is greater than a maximum voltage applied in the program operation, and the second voltage is greater than a maximum voltage applied in the erase operation,
in the voltage application process, the control circuit is configured to apply the first voltage to the ferroelectric layer by applying a first pulse voltage m times (m is an integer of 1 or more), and apply the second voltage to the ferroelectric layer by applying a second pulse voltage n times (n is an integer of 1 or more), and
when a pulse width of the first pulse voltage is set to a (μsec) and a pulse width of the second pulse voltage is set to b (μsec),
0.1
μsec
≦
a
×
m
<
250
⁢
μsec
(
Equation
⁢
1
)
0.1
μsec
≦
b
×
n
<
250
⁢
μsec
.
(
Equation
⁢
2
)

51 more elements

A method for controlling a memory system comprising:

a memory cell array with memory cells including a memory device arranged in a matrix;
and
a control circuit configured to control the memory cell array,
wherein
the memory device includes:
a semiconductor layer;
a gate electrode facing the semiconductor layer;
an insulating layer provided between the semiconductor layer and the gate electrode;
and
a ferroelectric layer provided between the insulating layer and the gate electrode and containing hafnium oxide,
the semiconductor layer contains silicon,
the insulating layer is in contact with the semiconductor layer,
the ferroelectric layer is in contact with the insulating layer,
a thickness of the ferroelectric layer is greater than 3 nm and less than 7 nm,
when the control circuit determines:
whether a number of times of executions of a program operation or an erase operation on the memory cells reaches a predetermined number of times;
or
whether a bit error rate is a predetermined rate or more,
the control circuit executes a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric layer so that Equation 1 and Equation 2 hold in the case where the number of times of executions reaches the predetermined number of times or the bit error rate is the predetermined rate or more,
wherein
the first voltage is greater than a maximum voltage applied in the program operation, and the second voltage is greater than a maximum voltage applied in the erase operation,
in the voltage application process, the control circuit is configured to apply the first voltage to the ferroelectric layer by applying a first pulse voltage m times (m is an integer of 1 or more), and apply the second voltage to the ferroelectric layer by applying a second pulse voltage n times (n is an integer of 1 or more), and
when a pulse width of the first pulse voltage is set to a (μsec) and a pulse width of the second pulse voltage is set to b (μsec),
0.1
μsec
≦
a
×
m
<
250
⁢
μsec
(
Equation
⁢
1
)
0.1
μsec
≦
b
×
n
<
250
⁢
μsec
.
(
Equation
⁢
2
)

51 more elements

A memory system comprising:

a plurality of memory cell arrays with a memory device arranged in a matrix;
and
a control circuit configured to control the plurality of memory cell arrays,
wherein
the memory device includes:
an oxide semiconductor layer;
a gate electrode facing the oxide semiconductor layer;
and
a ferroelectric layer provided between the oxide semiconductor layer and the gate electrode and containing hafnium oxide,
a thickness of the ferroelectric layer is greater than 1 nm and less than 30 nm,
when the control circuit determines:
whether a number of times of executions of a program operation or an erase operation on memory cells included in each of the plurality of memory cell arrays reaches a predetermined number of times, or
whether a bit error rate is a predetermined rate or more,
the control circuit executes a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric layer so that Equation 1 and Equation 2 hold in the case where the number of times of executions reaches the predetermined number of times or the bit error rate is the predetermined rate or more,
wherein
the first voltage is greater than a maximum voltage applied in the program operation, and the second voltage is greater than a maximum voltage applied in the erase operation,
in the voltage application process, the control circuit is configured to apply the first voltage to the ferroelectric layer by applying a first pulse voltage m times (m is an integer of 1 or more), and apply the second voltage to the ferroelectric layer by applying a second pulse voltage n times (n is an integer of 1 or more), and
when a pulse width of the first pulse voltage is set to a (μsec) and a pulse width of the second pulse voltage is set to b (μsec),
0.1
μsec
≦
a
×
m
<
250
⁢
μsec
(
Equation
⁢
1
)
0.1
μsec
≦
b
×
n
<
250
⁢
μsec
.
(
Equation
⁢
2
)

46 more elements

A method for controlling a memory system comprising:

a plurality of memory cell arrays with a memory device arranged in a matrix;
and
a control circuit configured to control the plurality of memory cell arrays,
wherein
the memory device includes:
an oxide semiconductor layer;
a gate electrode facing the oxide semiconductor layer;
and
a ferroelectric layer provided between the oxide semiconductor layer and the gate electrode and containing hafnium oxide,
a thickness of the ferroelectric layer is greater than 1 nm and less than 30 nm,
when the control circuit determines:
whether a number of times of executions of a program operation or an erase operation on the memory cell reaches a predetermined number of times;
or
whether a bit error rate is a predetermined rate or more,
the control circuit executes a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric layer so that Equation 1 and Equation 2 hold in the case where the number of times of executions reaches the predetermined number of times or the bit error rate is the predetermined rate or more,
wherein
the first voltage is greater than a maximum voltage applied in the program operation, and the second voltage is greater than a maximum voltage applied in the erase operation,
in the voltage application process, the control circuit is configured to apply the first voltage to the ferroelectric layer by applying a first pulse voltage m times (m is an integer of 1 or more), and apply the second voltage to the ferroelectric layer by applying a second pulse voltage n times (n is an integer of 1 or more), and
when a pulse width of the first pulse voltage is set to a (μsec) and a pulse width of the second pulse voltage is set to b (μsec),
0.1
μsec
≦
a
×
m
<
250
⁢
μsec
(
Equation
⁢
1
)
0.1
μsec
≦
b
×
n
<
250
⁢
μsec
.
(
Equation
⁢
2
)

47 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/406,338Filed 2 Dec 2025
Priority: 7 Jun 2023
Published: 26 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10B 51/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the memory core region
G11C 11/223
Using ferroelectric elements: using MOS with ferroelectric gate insulating film
G11C 11/2259
Auxiliary circuits: cell access
G11C 11/2273
Auxiliary circuits: reading or sensing circuits or methods

Family

Application63/506,675Us provisional application · filed 7 Jun 2023
Application19/406,338Continuation
US 2026/0089969 A1This patent

From the US filing history. Foreign family members aren’t listed.

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