Semiconductor memory device and memory chip including the same

A semiconductor memory device comprising:

• insulating layers and gate electrodes alternately stacked in a vertical direction;
• source/drain lines spaced apart in a second horizontal direction and extending in the vertical direction on sides of the insulating layers and the gate electrodes in a first horizontal direction;
• dielectric layers between the source/drain lines and the gate electrodes, the dielectric layers comprising a ferroelectric or antiferroelectric material;
• semiconductor layers between the source/drain lines and the dielectric layers;
• and
• first isolation patterns penetrating at least one of the dielectric layers and at least one of the semiconductor layers and spaced apart in the second horizontal direction.

A semiconductor memory chip comprising:

• a front-end-of-line (FEOL) structure comprising a semiconductor substrate and transistors on the semiconductor substrate;
• and
• a back-end-of-line (BEOL) structure on the FEOL structure, comprising a memory array electrically connected to the transistors, wherein the memory array comprises:
• insulating layers and gate electrodes alternately stacked in a vertical direction;
• source/drain lines spaced apart in a second horizontal direction and extending in the vertical direction on sides of the insulating layers and the gate electrodes in a first horizontal direction;
• at least one channel layer between the source/drain lines and the gate electrodes, the at least one channel layer comprising:
• a dielectric layer comprising a ferroelectric or antiferroelectric material;
• a gate dielectric layer;
• and
• a semiconductor layer;
• and
• first isolation patterns extending in the vertical direction, penetrating at least a portion of the at least one channel layer, and disposed between adjacent source/drain lines in the second horizontal direction.