Antiferroelectric memory device

A nonvolatile memory device including a plurality of nonvolatile memory elements, the nonvolatile memory elements comprising:

• a semiconductor layer including a metal oxide;
• a gate electrode facing the semiconductor layer;
• and
• a gate insulating layer made of an antiferroelectric material provided between the semiconductor layer and the gate electrode;
• wherein
• the electron affinity of a first material constituting the gate electrode is higher than the electron affinity of a second material constituting the semiconductor layer, and the second material is a p-type semiconductor.

A nonvolatile memory device including a plurality of nonvolatile memory elements, the nonvolatile memory elements comprising:

• a semiconductor layer including a metal oxide;
• a gate electrode facing the semiconductor layer;
• a gate insulating layer made of an antiferroelectric material provided between the semiconductor layer and the gate electrode;
• and
• an interface layer provided between the gate insulating layer and the gate electrode;
• wherein
• the electron affinity of a first material constituting the gate electrode is less than the electron affinity of a second material constituting the semiconductor layer, the second material is an n-type semiconductor, and the interface layer is made up of a silicon oxide.

A nonvolatile memory device including a plurality of nonvolatile memory elements, the nonvolatile memory elements comprising:

• a semiconductor layer including a metal oxide;
• a gate electrode facing the semiconductor layer;
• and
• a gate insulating layer made of an antiferroelectric material provided between the semiconductor layer and the gate electrode;
• wherein the metal oxide is a tin oxide or a composite oxide of In and Zn, and the electron affinity of a first material constituting the gate electrode is 4.9 eV or less.

A nonvolatile memory device including a plurality of nonvolatile memory elements, the nonvolatile memory elements comprising:

• a semiconductor layer including a metal oxide;
• a gate electrode facing the semiconductor layer;
• and
• a gate insulating layer made of an antiferroelectric material provided between the semiconductor layer and the gate electrode;
• wherein the metal oxide is a In oxide or a composite oxide of In, Ga, and Zn, and the electron affinity of a first material constituting the gate electrode is 4.3 eV or less.