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US 2026/0089954 A1Published application
Sub-block definition in a memory device using segmented source plates
AssigneeMicron Technology, Inc.
InventorsAaron S. Yip, Paolo Tessariol
Life of this patent
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Abstract
Control logic in a memory device causes a plurality of source control signals to be applied to a plurality of deintegrated source segments of a first block of a plurality of blocks of a memory array of a memory device to selectively activate a plurality of sub-blocks of the first block and programs a plurality of select gate devices in a plurality of logical select gate layers spanning the plurality of sub-blocks and positioned at a drain-side of the first block of the memory array with a threshold voltage pattern.
Claims20
A memory device comprising:
- a memory array comprising a plurality of blocks, each block comprising a plurality of sub-blocks;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- causing respective source control signals to be applied to a plurality of deintegrated source segments of a first block of the plurality of blocks of the memory array to selectively activate one or more of the plurality of sub-blocks of the first block during a memory access operation.
1 more element
A memory device comprising:
- a memory array comprising a block, the block comprising a plurality of wordlines and a number of sub-blocks each comprising a plurality of memory cells associated with the plurality of wordlines, wherein the memory array further comprises:
- a number of deintegrated source segments, wherein each source segment is associated with a respective sub-block of the plurality of sub-blocks, wherein the deintegrated source segments are to selectively activate one or more of the number of sub-blocks during a memory access operation.
A memory device comprising:
- a memory array comprising a plurality of strings of memory cells, wherein each string of memory cells is associated with a respective source segment of a plurality of deintegrated source segments;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- causing respective source control signals to be applied to the plurality of deintegrated source segments of the memory array to selectively activate one or more of the plurality of strings of memory cells during a memory access operation.
1 more element
Dependencies are inferred from the claim text.