Non-volatile memory device, method of manufacturing the same, and memory system including the same

A non-volatile memory device comprising:

• a peripheral circuit structure comprising a peripheral circuit, the peripheral circuit including a plurality of peripheral circuit transistors;
• a first cell array structure on the peripheral circuit structure, the first cell array structure electrically connected to the peripheral circuit structure, the first cell array structure comprising a first bit line, a first bit line wiring insulation layer surrounding the first bit line, a first common source line layer, a first cell stack being between the first bit line and the first common source line layer in a vertical direction, the first cell stack including a plurality of first gate electrodes and a plurality of first interlayer insulation layers alternating in the vertical direction, and a plurality of first channel structures extending through the first cell stack into the first bit line wiring insulation layer;
• and
• a second cell array structure on the first cell array structure, the second cell array structure electrically connected to the first cell array structure, the second cell array structure comprising a second common source line layer, a second bit line, a second bit line wiring insulation layer surrounding the second bit line, a second cell stack being between the second common source line layer and the second bit line in the vertical direction, the second cell stack including a plurality of second gate electrodes and a plurality of second interlayer insulation layers alternating in the vertical direction, and a plurality of second channel structures extending through the second cell stack into the second bit line wiring insulation layer, the first common source line layer and the second common source line layer being between the first cell stack and the second cell stack,
• each of the plurality of first channel structures comprises a first channel layer, a first bit line pad, and a first gate insulation layer, the first channel layer electrically connected to the first common source line layer, the first bit line pad electrically connecting the first channel layer and the first bit line, the first bit line pad being adjacent to one end of the first channel layer facing the first bit line, and the first gate insulation layer covering the first channel layer and the first bit line pad,
• each of the plurality of second channel structures comprises a second channel layer, a second bit line pad, and a second gate insulation layer, the second channel layer electrically connected to the second common source line layer, the second bit line pad electrically connecting the second channel layer and the second bit line, the second bit line pad being adjacent to one end of the second channel layer facing the second bit line, and the second gate insulation layer covering the second channel layer and the second bit line pad,
• the first gate insulation layer comprises a first insulation protrusion, the first insulation protrusion being at a boundary between the first bit line wiring insulation layer and the first cell stack, the first insulation protrusion protruding in a horizontal direction further than a portion of the first gate insulation layer penetrating through the first cell stack, and
• the second gate insulation layer comprises a second insulation protrusion, the second insulating protrusion being at a boundary between the second bit line wiring insulation layer and the second cell stack, the second insulation protrusion protruding in the horizontal direction further than a portion of the second gate insulation layer penetrating through the second cell stack.

A memory system comprising:

• a non-volatile memory device comprising
• a peripheral circuit structure, the peripheral circuit structure comprising a peripheral circuit, the peripheral circuit including a plurality of peripheral circuit transistors,
• a first cell array structure on the peripheral circuit structure,
• a second cell array structure on the first cell array structure, and
• an input/output pad disposed on the second cell array structure, wherein each of the first cell array structure and the second cell array structure comprises a common source line layer, a bit line, a bit line wiring insulation layer surrounding the bit line, a cell stack being between the common source line layer and the bit line in a vertical direction, the cell stack including a plurality of gate electrodes and a plurality of interlayer insulation layers alternating in the vertical direction, and a plurality of channel structures extending through the cell stack into the bit line wiring insulation layer;
• and
• a memory controller electrically connected to the non-volatile memory device through the input/output pad and configured to control the non-volatile memory device,
• wherein the common source line layer of the first cell array structure and the common source line layer of the second cell array structure are arranged between the cell stack of the first cell array structure and the cell stack of the second cell array structure,
• each of the plurality of channel structures included in each of the first cell array structure and the second cell array structure comprises a channel layer, a bit line pad, and a gate insulation layer, the channel layer electrically connected to the common source line layer, the bit line pad electrically connecting the channel layer to the bit line, the bit line pad being adjacent to one end of the channel layer facing the bit line, and the gate insulation layer covering the channel layer and the bit line pad, and
• the gate insulation layer included in each of the first cell array structure and the second cell array structure comprises an insulation protrusion, the insulation protrusion being at a boundary between the bit line wiring insulation layer and the cell stack, the insulation protrusion protruding in a horizontal direction further than a portion of the gate insulation layer penetrating through the cell stack.