Memory Circuitry And Methods Used In Forming Memory Circuitry

Memory circuitry comprising:

• vertically-alternating insulative tiers and memory-cell tiers;
• memory cells in the memory-cell tiers that individually comprise a horizontal transistor, a capacitor that is on a capacitor side of the horizontal transistor, and part of a digitline that is on a digitline side of the horizontal transistor;
• the capacitor, the horizontal transistor, and the digitline part being horizontally spaced relative one another along an axis;
• the horizontal transistor having a gate that comprises a top gate and a bottom gate having channel material therebetween, immediately-vertically-adjacent of the memory-cell tiers comprising an upper memory-cell tier and a lower memory-cell tier;
• and
• insulator material that extends from horizontally aside the capacitor side of the top gate in the lower memory-cell tier through the insulative tier that is between the upper and lower memory-cell tiers to horizontally aside the capacitor side of the bottom gate in the upper memory-cell tier, the insulator material in the upper memory-cell tier and in the lower memory-cell tier having a laterally-outer linearly-straight surface in a vertical cross-section that is through and horizontally-elongated along the axis;
• the laterally-outer linearly-straight surface being one of vertical, angled from vertical toward the capacitor side by no more than 40°, or angled from vertical away from the capacitor side by no more than 30°.

Memory circuitry comprising:

• vertically-alternating insulative tiers comprising silicon dioxide and memory-cell tiers;
• memory cells in the memory-cell tiers that individually comprise a horizontal transistor, a capacitor that is on a capacitor side of the horizontal transistor, and part of a digitline that is on a digitline side of the horizontal transistor;
• the capacitor, the horizontal transistor, and the digitline part being horizontally spaced relative one another along an axis, immediately-vertically-adjacent of the memory-cell tiers comprising an upper memory-cell tier and a lower memory-cell tier;
• the horizontal transistor having a gate that comprises a top gate that is part of one of a plurality of top horizontal conductive access lines and comprises a bottom gate that is part of one of a plurality of bottom horizontal conductive access lines, the one top horizontal conductive access line and the one bottom horizontal conductive access line together directly electrically coupling together multiple of the top and bottom gates of different ones of the horizontal transistors that are in the same memory-cell tier;
• and
• silicon nitride that extends from horizontally aside the capacitor side of the top gate in the lower memory-cell tier through the silicon dioxide of the insulative tier that is between the upper and lower memory-cell tiers to horizontally aside the capacitor side of the bottom gate in the upper memory-cell tier, the silicon nitride in the upper memory-cell tier and in the lower memory-cell tier having a laterally-outer linearly-straight surface in a vertical cross-section that is through and horizontally-elongated along the axis;
• the laterally-outer linearly-straight surface being one of vertical, angled from vertical away from the capacitor side by no more than 40°, or angled from vertical toward the capacitor side by no more than 30°.