Semiconductor device

A semiconductor device, comprising:

• a cell vertical active pattern and a peripheral vertical active pattern disposed at the same vertical level;
• a cell upper extended source/drain pattern and a cell contact plug sequentially stacked on the cell vertical active pattern;
• a peripheral upper extended source/drain pattern and a peripheral contact plug sequentially stacked on the peripheral vertical active pattern;
• a cell isolation pattern on a side surface of the cell upper extended source/drain pattern and a side surface of the cell contact plug;
• a peripheral isolation pattern on a side surface of the peripheral upper extended source/drain pattern and a side surface of the peripheral contact plug;
• and
• an upper interconnection on the peripheral contact plug and the peripheral isolation pattern,
• wherein the cell contact plug includes a cell lower conductive layer and a cell upper conductive layer sequentially stacked,
• wherein the peripheral contact plug includes a peripheral lower conductive layer and a peripheral upper conductive layer sequentially stacked,
• wherein the cell lower conductive layer and the peripheral lower conductive layer include a first conductive material,
• wherein the cell upper conductive layer and the peripheral upper conductive layer include a second conductive material different from the first conductive material, and
• wherein the upper interconnection includes a third conductive material different from the first conductive material and different from the second conductive material.

A semiconductor device, comprising:

• a first structure including a memory region and a peripheral region;
• and
• a second structure vertically overlapping the first structure and including a peripheral circuit,
• wherein the memory region includes:
• a cell vertical active pattern;
• a cell gate electrode having a side surface facing a side surface of the cell vertical active pattern;
• a cell upper source/drain pattern and a cell contact plug disposed on the cell vertical active pattern, the cell upper source/drain pattern being between the cell vertical active pattern and the cell contact plug;
• a cell isolation pattern on side surfaces of the cell upper source/drain pattern and the cell contact plug;
• and
• a data storage structure on the cell contact plug and the cell isolation pattern,
• wherein the peripheral region includes:
• a peripheral vertical active pattern;
• a peripheral gate electrode having a side surface facing a side surface of the peripheral vertical active pattern;
• a peripheral upper source/drain pattern and a peripheral contact plug disposed on the peripheral vertical active pattern, the peripheral upper source/drain pattern being between the peripheral vertical active pattern and the peripheral contact plug;
• a peripheral isolation pattern on a side surface of the peripheral upper source/drain pattern and a side surface of the peripheral contact plug;
• and
• an upper interconnection on the peripheral contact plug and the peripheral isolation pattern,
• wherein the cell upper source/drain pattern includes a first cell source/drain layer and a second cell source/drain layer sequentially stacked,
• wherein the peripheral upper source/drain pattern includes a first peripheral source/drain layer and a second peripheral source/drain layer sequentially stacked,
• wherein the peripheral circuit includes a first lower transistor vertically overlapping the memory region and a second lower transistor vertically overlapping the peripheral region,
• wherein the cell contact plug includes a cell lower conductive layer and a cell upper conductive layer sequentially stacked,
• wherein the peripheral contact plug includes a peripheral lower conductive layer and a peripheral upper conductive layer sequentially stacked,
• wherein the cell lower conductive layer and the peripheral lower conductive layer include a first conductive material,
• wherein the cell upper conductive layer and the peripheral upper conductive layer include a second conductive material different from the first conductive material, and
• wherein the upper interconnection includes a third conductive material different from the first and second conductive materials.