Memory device, fabrication method and memory system

A fabrication method of a memory device, comprising:

• providing semiconductor bodies extending in a first direction, a semiconductor body comprising a first end and a second end disposed opposite to each other in the first direction, wherein a first dielectric material is filled between at least two adjacent ones of the semiconductor bodies comprising the semiconductor body, a second direction intersects with the first direction, a third direction intersects with the second direction, and a plane formed by the second direction and the third direction intersects with the first direction;
• etching the first dielectric material between first ends of the semiconductor bodies adjacent in the third direction to form a first trench extending in the second direction, wherein sidewalls of the first trench expose a cavity between the first ends adjacent in the second direction;
• forming a first dielectric layer on the sidewalls of the first trench and inner walls of the cavity, wherein the first dielectric layer at least partially covers sidewalls of the first end of the semiconductor body extending in the first direction;
• and
• filling the first trench with a second dielectric material to form a second dielectric layer in both the trench and the cavity.

A memory system, comprising:

• a memory device, comprising:
• semiconductor bodies extending in a first direction, a semiconductor body comprising a first end and a second end disposed opposite to each other in the first direction;
• a bit line extending in a second direction intersecting the first direction, the bit line being located on a side of the semiconductor body proximate to the first end in the first direction and coupled to the first end of the semiconductor body;
• a first dielectric layer located between at least two adjacent ones of the semiconductor bodies comprising the semiconductor body, the first dielectric layer at least partially covering sidewalls of the first end of the semiconductor body extending in the first direction;
• and
• a second dielectric layer located between the at least two adjacent ones of the semiconductor bodies, wherein the first dielectric layer is located between the second dielectric layer and the semiconductor body;
• and
• a memory controller coupled to and controlling the memory device.