US 2026/0089925 A1 · SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

Abstract

A semiconductor memory device includes a substrate including first and second active regions, first and second device isolation structures disposed in the substrate, the first device isolation structure delimiting the first active region, the second active region being between the first device isolation structure and the second device isolation structure, a word line in the substrate, crossing the first and second active regions, and overlapping the second device isolation structure, and a word line connection contact plug spaced apart from the second active region and connected to an end portion of the word line. The word line includes first, second and third conductive patterns. The second conductive pattern is spaced apart from the word line connection contact plug.

Claims21

Dependent claims

A semiconductor memory device comprising:

a substrate including a first active region and a second active region;
a first device isolation structure and a second device isolation structure disposed in the substrate, the first device isolation structure delimiting the first active region, the second active region being between the first device isolation structure and the second device isolation structure;
a word line in the substrate, crossing the first active region and the second active region, and overlapping the second device isolation structure;
and
a word line connection contact plug spaced apart from the second active region and connected to an end portion of the word line,
wherein the word line comprises:
a first conductive pattern;
a second conductive pattern on the first conductive pattern and covering the first active region and the second active region;
and
a third conductive pattern on the second conductive pattern and covering the first active region,
wherein the second conductive pattern is spaced apart from the word line connection contact plug.

8 more elements

A semiconductor memory device comprising:

a substrate including a peripheral region, a dummy region, and a cell region sequentially arranged in a first direction;
a first device isolation structure disposed in the cell region to delimit first active regions;
a second device isolation structure disposed in the dummy region and the peripheral region to delimit second active regions;
word lines disposed in the dummy region and the cell region to cross the first active regions and the second active regions in the first direction;
and
bit lines disposed on the cell region, the bit lines being connected to the first active regions and extending in a second direction orthogonal to the first direction,
wherein each of the word lines comprises:
a first conductive pattern comprising a first portion on the second device isolation structure and the second active regions, and a second portion on the first active regions;
a second conductive pattern on the second portion of the first conductive pattern;
and
a third conductive pattern interposed between the first conductive pattern and the second conductive pattern,
wherein the third conductive pattern extends to cover an end portion of the first portion of the first conductive pattern, and
wherein a side surface of the third conductive pattern that is extended is placed adjacent to an edge of the second device isolation structure.

10 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device and method of fabricating the same

Life of this patent

Semiconductor memory device and method of fabricating the same

Life of this patent

Abstract

Claims21