Semiconductor memory device

A semiconductor memory device including a plurality of SRAM cells,

• each of the SRAM cells comprising:
• a first transistor having a source connected to a first power source for supplying a first power supply voltage, a drain connected to a first node, and a gate connected to a second node;
• a second transistor having a source connected to the first power source, a drain connected to the second node, and a gate connected to the first node;
• a third transistor having a source connected to a second power source for supplying a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node;
• a fourth transistor having a source connected to the second power source, a drain connected to the second node, and a gate connected to the first node;
• a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line;
• and
• a sixth transistor having a source connected to a second bit line forming a complementary bit line pair together with the first bit line, a drain connected to the second node, and a gate connected to the word line,
• the plurality of SRAM cells including:
• a first SRAM cell;
• and
• a second SRAM cell aligned with the first SRAM cell in a first direction,
• the first bit line of the first SRAM cell including a first line formed in a metal interconnect layer above the first to sixth transistors, the first line extending in a second direction,
• the second bit line of the first SRAM cell including a second line formed in the metal interconnect layer, the second line extending in the second direction,
• the first SRAM cell comprising:
• a first active region forming a channel, the source, and the drain of the third transistor of the first SRAM cell, and including a nanosheet extending in the second direction as the channel;
• a second active region forming a channel, the source, and the drain of the fourth transistor of the first SRAM cell, and including a nanosheet extending in the second direction as the channel;
• a first power supply line formed in a first back interconnect layer on a back side of the first to sixth transistors, the first power supply line extending in the second direction and connected to the second power source;
• a second power supply line formed in the first back interconnect layer, the second power supply line extending in the second direction and connected to the second power source;
• a first via arranged at a position where a first region forming the source of the third transistor in the first active region and the first power supply line overlap each other, the first via connecting the first region and the first power supply line;
• and
• a second via arranged at a position where a second region forming the source of the fourth transistor in the second active region and the second power supply line overlap each other, the second via connecting the second region and the second power supply line,
• the first bit line of the second SRAM cell including a third line formed in the first back interconnect layer, the third line extending in the second direction,
• the second bit line of the second SRAM cell including a fourth line formed in the first back interconnect layer, the fourth line extending in the second direction,
• the second SRAM cell comprising:
• a third active region forming a channel, the source, and the drain of the third transistor of the second SRAM cell, and including a nanosheet extending in the second direction as the channel;
• a fourth active region forming a channel, the source, and the drain of the fourth transistor of the second SRAM cell, and including a nanosheet extending in the second direction as the channel;
• a third via arranged at a position where a third region forming the source of the third transistor in the third active region and the third line overlap each other, the third via connecting the third region and the third line;
• a fourth via arranged at a position where a fourth region forming the source of the fourth transistor in the fourth active region and the fourth line overlap each other, the fourth via connecting the fourth region and the fourth line;
• and
• a third power supply line formed in the metal interconnect layer, the third power supply line extending in the second direction and connected to the second power source.