Warped Filter Architecture with Reduced Processing Rate Systems and Methods

Filter circuitry configured to:

• receive an input signal at a first sampling rate and a first bit-depth;
• convert the first sampling rate and the first bit-depth of the input signal to a second sampling rate less than the first sampling rate and a second bit-depth greater than the first bit-depth to generate an intermediate signal;
• modulate the intermediate signal to generate a filter input signal comprising a processing rate less than the first sampling rate;
• filter, via a warped finite impulse response filter, the filter input signal based on a set of filter coefficients to generate a filtered signal;
• and
• output the filtered signal.

A non-transitory, machine-readable medium comprising instructions, wherein, when executed by one or more processors, the instructions cause the one or more processors to control operations of filter circuitry or to perform the operations, the operations comprising:

• receiving an input signal at a first sampling rate;
• resampling the input signal to generate an intermediate signal at a second sampling rate less than the first sampling rate;
• modulating the intermediate signal to generate a filter input signal comprising a processing rate less than the first sampling rate;
• filtering, via a warped finite impulse response filter and at the processing rate, the filter input signal based on a set of filter coefficients to generate a filtered signal;
• and
• outputting the filtered signal.