Strong puf circuit with good stability and anti-ml attack capacity

A strong PUF circuit with good stability and anti-ML attack capacity, comprising:

• n delay modules, n−1 interconnection modules, an arbiter array, and an XOR gate, wherein n is an integer greater than or equal to 1, each of the n delay modules is implemented based on a bias source structure, and each of the n delay modules has 2×d input terminals, l selection terminals and d output terminals,
• wherein d=2i, and i is an integer greater than or equal to 2, l is an integer greater than or equal to 1,
• wherein each of the n−1 interconnection modules has d input terminals and 2×d output terminals, the arbiter array has d input terminals and d/2 output terminals, and the XOR gate has d/2 input terminals and an output terminal;
• wherein when n=1, the d output terminals of the nth delay module are connected to the d input terminals of the arbiter array in one-to-one correspondence;
• wherein when n=2, the d output terminals of the first delay module are connected to the d input terminals of the first interconnection module in one-to-one correspondence, the 2×d output terminals of the first interconnection module are connected to the 2×d input terminals of the second delay module in one-to-one correspondence, and the d output terminals of the nth delay module are connected to the d input terminals of the arbiter array in one-to-one correspondence;
• wherein when n is greater than or equal to 3, the d output terminals of the pth delay module are connected to the d input terminals of the pth interconnection module in one-to-one correspondence, the 2×d output terminals of the pth interconnection module are connected to the 2×d input terminals of the (p+1)th delay module in one-to-one correspondence, wherein p=1, 2, . . . , n−1, and the d output terminals of the nth delay module are connected to the d input terminals of the arbiter array in one-to-one correspondence;
• wherein the d/2 output terminals of the arbiter array are connected to the d/2 input terminals of the XOR gate in one-to-one correspondence;
• wherein the l selection terminals of the n delay modules form n×l challenge terminals of the strong PUF circuit with an anti-ML attack capacity and allow n×l challenge signals to be input thereto, the output terminal of the XOR gate is an output terminal of the strong PUF circuit with an anti-ML attack capacity and used for outputting PUF responses, and the 2×d input terminals of the first delay module are 2×d trigger terminals of the strong PUF circuit with an anti-ML attack capacity and allow 2×d input signals to be input thereto as trigger signals;
• wherein l challenge signals are input to the l selection terminals of each delay module, 2×d input signals are input to the 2×d input terminals of each delay module, and each delay module from the first delay module to the (n−1)th delay module combines every two of the 2×d input signals input to the 2×d input terminals thereof under the control of the l challenge signals input to the l selection terminals thereof to form d groups of input signals to be screened, wherein the input signal with a large delay is screened out of each of the d/2 groups, the input signal with a small delay is screened out of each of the other d/2 groups, d output signals are generated according to the d/2 input signals with a large delay and the d/2 input signals with a small delay and used as d input signals of the interconnection module connected to the delay module;
• wherein the nth delay module combines every two of the 2×d input signals input to the 2×d input terminals thereof under the control of the l challenge signals input to the l selection terminals thereof to form d groups of input signals, wherein the input signal with a large delay is screened out of each of the d/2 groups, the input signal with a small delay is screened out of each of the other d/2 groups, and d output signals are generated according to the d/2 input signals with a large delay and the d/2 input signals with a small delay, which are used as d input signals of the arbiter array and input to the d input terminals of the arbiter array in one-to-one correspondence by means of the d output terminals of the nth delay module;
• wherein the arbiter array combines every two of the d input signals input to the d input terminals thereof to form d/2 groups of input signals for arbitration to obtain d/2 arbitration signals, which are used as d/2 input signals of the XOR gate and input to the d/2 input terminals of the XOR gate in one-to-one correspondence by means of the d/2 output terminals of the arbiter array;
• the XOR gate performs an XOR operation on the d/2 input signals input to the d/2 input terminals thereof to obtain a PUF response, which is output by means of the output terminal of the XOR gate;
• and
• wherein each interconnection module is used for duplicating the d input signals input to the d input terminals thereof to generate 2×d output signals, which are used as 2×d input signals of the delay module connected to the interconnection module and output to the 2×d input terminals of the delay module connected to the interconnection module in one-to-one correspondence by means of the 2×d output terminals of the interconnection module.