Acceleration of cryptographic operations

A circuit arrangement comprising:

• a first plurality of cryptographic accelerators (102, 104, 106);
• a second plurality of cryptographic accelerators (108, 110);
• a memory (126, 128);
• one or more direct memory access (DMA) controllers (130) coupled to the memory and to the first plurality of cryptographic accelerators;
• and
• a first processor (116) configured to, in response to requests to perform cryptographic operations from a plurality of agent processors, signal the first and second pluralities cryptographic accelerators to commence performing the cryptographic operations according to the requests;
• and
• wherein the one or more DMA controllers are configured to move data between the memory and the first plurality of cryptographic accelerators, and the second plurality of cryptographic accelerators is configured to bypass the one or more DMA controllers in moving data between the memory and the second plurality of cryptographic accelerators.