US 2026/0088809 A1Published application

Voltage buffer

AssigneeSemiconductor Components Industries, LLC

InventorsShanil KURIACHAN, Simon Charles DENNY

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Abstract

Systems, devices, and methods are provided for an improved voltage buffer. Improved voltage buffers may include an output circuit operating in a first voltage domain, and an input circuit operating in a second voltage domain and receiving a reference voltage and feedback signal. The second voltage domain may have a lower voltage than the first voltage domain. A bias circuit coupled between the input and output circuits may bias operation of the output circuit. An error signal from the input circuit may adjust the bias of the output circuit. A level shifting circuit may translate the adjusted bias signal from the second to the first voltage domain. The bias circuit may be controlled according to transistors having opposite VGS temperature curves. Advantageously, a reduced portion of the voltage buffer may be exposed to over-voltage stress, and the voltage buffer may be more resistant to temperature-based fluctuations in output voltage.

Claims20

Dependent claims

A voltage buffer, comprising:

an output circuit operable in a first voltage domain and comprising an output node, wherein the output circuit is controllable to provide an output voltage at the output node;
an input circuit operable in a second voltage domain and configured to receive an input voltage reference and a feedback signal, wherein the input circuit is configured to generate an error signal based on the feedback signal and the input voltage reference, and wherein the first voltage domain is a higher voltage than the second voltage domain;
a feedback circuit coupled with the output circuit and the input circuit, wherein the feedback circuit is configured to generate the feedback signal based on the output voltage;
a buffer bias circuit coupled with the input circuit, wherein the buffer bias circuit is configured to provide a bias signal and wherein the error signal adjusts the bias signal provided by the buffer bias circuit;
and
a level shifting circuit operable in the first voltage domain and coupled with the buffer bias circuit and the output circuit, wherein the level shifting circuit is configured to translate the adjusted bias signal from the second voltage domain to the first voltage domain, and wherein the output circuit is controllable by the translated adjusted bias signal.

3 more elements

A voltage buffer, comprising:

a feedback circuit;
an error amplifier comprising a first input, a second input, and an error output, wherein the first input is coupled with a voltage reference, the second input is coupled with the feedback circuit, and wherein the error amplifier is further coupled to a second voltage supply;
an output circuit comprising a sourcing transistor coupled in series with a sinking transistor and a first voltage supply, wherein:
the sourcing transistor and sinking transistor are coupled at a first output node;
the first output node is coupled with the feedback circuit;
and
a first voltage provided by the first voltage supply is greater than a second voltage provided by the second voltage supply;
a level shifting circuit comprising a third input and a second output, wherein:
the level shifting circuit is coupled with the first voltage supply;
the second output is coupled with the sourcing transistor;
and
the level shifting circuit is configured to receive a voltage signal on the third input, increase a voltage level of the received voltage signal, and provide the increased voltage signal on the second output;
and
a buffer bias circuit coupled with the error output and the third input, wherein the buffer bias circuit is configured to control an operating point of the sourcing transistor and an operating point of the sinking transistor.

11 more elements

A voltage buffer, comprising:

an input circuit configured to receive an input voltage reference, receive a feedback signal, and generate an error signal based on the feedback signal and the input voltage reference;
an output circuit comprising an output node, wherein the output circuit is controllable to provide an output voltage at the output node;
a feedback circuit coupled with the output circuit and the input circuit, wherein the feedback circuit is configured to generate the feedback signal based on the output voltage;
and
a buffer bias circuit coupled with the input circuit and the output circuit, wherein:
the buffer bias circuit comprises a first NMOS transistor coupled in parallel with a first PMOS transistor, wherein a gate terminal of the NMOS transistor is coupled with an N-bias circuit and a gate terminal of the PMOS transistor is coupled with a P-bias circuit;
the P-bias circuit comprises a diode-connected second PMOS transistor coupled in series with a diode-connected third PMOS transistor;
the second PMOS transistor has a source-to-gate voltage temperature curve having a positive slope;
and
the third PMOS transistor has a source-to-gate voltage temperature curve having a negative slope.

7 more elements

Dependencies are inferred from the claim text.