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US 2026/0088099 A1Published application
Semiconductor memory device
AssigneeKioxia Corporation
InventorYasuhiro SHIINO
Life of this patent
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Abstract
A semiconductor memory device includes a memory block including first and second sub memory blocks, a bit line and a source line, and a control circuit. The first and the second sub memory blocks include first and second memory cells and first and second word lines, respectively. The control circuit performs, in an erase operation on the memory block, a first determination operation to determine a write state of the second memory cell, a first erase operation performed when the second memory cell is in the write state, and a second erase operation performed when the second memory cell is in an erase state.
Claims17
A semiconductor memory device comprising:
- a substrate;
- a memory block including a first sub memory block and a second sub memory block arranged in a first direction intersecting with a surface of the substrate;
- a bit line disposed on one side in the first direction with respect to the memory block;
- a source line disposed on the other side in the first direction with respect to the memory block;
- and
- a control circuit that controls the memory block, wherein
- the first sub memory block includes:
- a first memory cell electrically connected to the bit line and the source line;
- and
- a first word line electrically connected to the first memory cell,
- the second sub memory block includes:
- a second memory cell electrically connected to the bit line and the source line;
- and
- a second word line electrically connected to the second memory cell,
- the control circuit is configured to be able to perform, in an erase operation on the memory block:
- a first determination operation to determine whether or not the second memory cell is in a write state;
- a first erase operation performed when the second memory cell is in the write state;
- and
- a second erase operation performed when the second memory cell is in an erase state,
- in the first erase operation:
- an erase voltage is applied to one or both of the bit line and the source line;
- and
- a select erase voltage lower than the erase voltage is applied to the first word line and the second word line, and
- in the second erase operation:
- the erase voltage is applied to one or both of the bit line and the source line;
- the select erase voltage is applied to the first word line;
- and
- an unselect erase voltage lower than the erase voltage and higher than the select erase voltage is applied to the second word line.
25 more elements
A semiconductor memory device comprising:
- a substrate;
- a memory block including a first sub memory block and a second sub memory block arranged in a first direction intersecting with a surface of the substrate;
- a bit line disposed on one side in the first direction with respect to the memory block;
- a source line disposed on the other side in the first direction with respect to the memory block;
- and
- a control circuit that controls the memory block, wherein
- the first sub memory block includes:
- a plurality of first memory cells electrically connected to the bit line and the source line;
- and
- a plurality of first word lines electrically connected to the plurality of first memory cells,
- the second sub memory block includes:
- a plurality of second memory cells electrically connected to the bit line and the source line;
- and
- a plurality of second word lines electrically connected to the plurality of second memory cells,
- the control circuit is configured to be able to perform, in an erase operation on the memory block:
- a first determination operation to determine whether or not at least one of the plurality of second memory cells is in a write state;
- a second determination operation to determine whether or not at least one of the plurality of second memory cells is in an erase state;
- a third determination operation to determine whether or not at least one of the plurality of first memory cells is in the erase state;
- a first pre-erase write operation performed when at least one of the plurality of second memory cells is in the write state and at least one of the plurality of second memory cells is in the erase state;
- and
- a second pre-erase write operation performed when at least one of the plurality of first memory cells is in the write state and at least one of the plurality of first memory cells is in the erase state,
- in the first pre-erase write operation:
- a program voltage is applied to the plurality of second word lines;
- and
- an unselect write voltage lower than the program voltage is applied to the plurality of first word lines, and
- in the second pre-erase write operation:
- the program voltage is applied to the plurality of first word lines;
- and
- the unselect write voltage is applied to the plurality of second word lines.
26 more elements
Dependencies are inferred from the claim text.