Memory array and methods of operation

A device comprising:

• memory cells arranged in rows and columns, wherein respective ones of the memory cells have a select transistor and a sense transistor;
• memory sections, wherein respective ones of the memory sections includes a plurality of memory cells and a section select transistor;
• a source line physically coupled to a source terminal of a section select transistor;
• a wordline physically coupled to a gate of a section select transistor and a gate of a select transistor;
• and
• a sense gate line physically coupled to a gate of a sense transistor.

A system comprising:

• a memory device that includes:
• memory cells arranged in rows and columns, wherein respective ones of the memory cells have a select transistor and a sense transistor;
• memory sections, wherein respective ones of the memory sections includes a plurality of memory cells and a section select transistor;
• a source line physically coupled to a source terminal of a section select transistor;
• a bitline physically coupled to a drain of a select transistor;
• a wordline physically coupled to a gate of a section select transistor and a gate of a select transistor;
• and
• a sense gate line physically coupled to a gate of a sense transistor;
• and
• instructions stored in a machine-readable medium that, when executed, are configured to cause a processor to perform an erase operation on a first memory section in a first group of memory sections, the erase operation comprising:
• applying a low voltage to the source line;
• applying a low voltage to the bitline;
• applying a high voltage to the sense gate line;
• and
• applying a middle voltage to the wordline,
• wherein the high voltage is higher than the low voltage and the middle voltage is between the low voltage and the high voltage.