Managing program time in memory devices

A memory device, comprising:

• a memory array comprising a first word line and at least one second word line;
• and
• a peripheral circuit coupled to the memory array, wherein the peripheral circuit is configured to perform operations comprising:
• during a first loop of a program operation to program memory cells coupled to the first word line:
• applying a first program voltage to the first word line;
• applying, during a first stage of the first loop, a first pass voltage to the at least one second word line;
• and
• applying, during a second stage of the first loop, a second pass voltage to the at least one second word line, wherein the second stage is after the first stage;
• and
• during a second loop of the program operation:
• applying a second program voltage to the first word line;
• applying, during a first stage of the second loop, a third pass voltage to the at least one second word line;
• and
• applying, during a second stage of the second loop, a fourth pass voltage to the at least one second word line,
• wherein the second loop is after the first loop, the second program voltage is higher than the first program voltage, a difference between the fourth pass voltage and the third pass voltage is greater than a difference between the second pass voltage and the first pass voltage.

A memory system, comprising:

• a memory device, comprising:
• a memory array comprising a first word line and at least one second word line;
• a peripheral circuit coupled to the memory array, wherein the peripheral circuit is configured to perform operations comprising:
• during a first loop of a program operation to program memory cells coupled to the first word line:
• applying a first program voltage to the first word line;
• applying, during a first stage of the first loop, a first pass voltage to the at least one second word line;
• and
• applying, during a second stage of the first loop, a second pass voltage to the at least one second word line, wherein the second stage is after the first stage;
• and
• during a second loop of the program operation:
• applying a second program voltage to the first word line;
• applying, during a first stage of the second loop, a third pass voltage to the at least one second word line;
• and
• applying, during a second stage of the second loop, a fourth pass voltage to the at least one second word line,
• wherein the second loop is after the first loop, the second program voltage is higher than the first program voltage, a difference between the fourth pass voltage and the third pass voltage is greater than a difference between the second pass voltage and the first pass voltage;
• and
• a memory controller coupled to the memory device and configured to control the memory device.