Managing program time in memory devices

A memory device, comprising:

• a memory array comprising a first word line and at least one second word line;
• and
• a peripheral circuit coupled to the memory array, wherein the peripheral circuit is configured to perform operations comprising:
• during a first loop of a first program operation to program memory cells coupled to the first word line:
• applying a first program voltage to the first word line;
• applying, during a first stage of the first loop, a first pass voltage to the at least one second word line;
• and
• applying, during a second stage of the first loop, a second pass voltage to the at least one second word line, wherein the second stage is after the first stage;
• and
• during a second loop of the first program operation:
• applying a second program voltage to the first word line;
• applying, during a first stage of the second loop, a third pass voltage to the at least one second word line;
• and
• applying, during a second stage of the second loop, a fourth pass voltage to the at least one second word line,
• during a third loop of the first program operation:
• applying a third program voltage to the first word line;
• applying, during a first stage of the third loop, a fifth pass voltage to the at least one second word line;
• and
• applying, during a second stage of the third loop, a sixth pass voltage to the at least one second word line,
• wherein the second loop is after the first loop, the third loop is after the second loop, the second program voltage is higher than the first program voltage, and the third program voltage is higher than the second program voltage, and
• wherein the third pass voltage is lower than the first pass voltage, and the fifth pass voltage is higher than the third pass voltage.

A memory system, comprising:

• a memory device, comprising:
• a memory array comprising a first word line and at least one second word line;
• a peripheral circuit coupled to the memory array, wherein the peripheral circuit is configured to perform operations comprising:
• during a first loop of a first program operation to program memory cells coupled to the first word line:
• applying a first program voltage to the first word line;
• applying, during a first stage of the first loop, a first pass voltage to the least one second word line;
• and
• applying, during a second stage of the first loop, a second pass voltage to the at least one second word line, wherein the second stage is after the first stage;
• and
• during a second loop of the first program operation:
• applying a second program voltage to the first word line;
• applying, during a first stage of the second loop, a third pass voltage to the at least one second word line;
• and
• applying, during a second stage of the second loop, a fourth pass voltage to the at least one second word line,
• during a third loop of the first program operation:
• applying a third program voltage to the first word line;
• applying, during a first stage of the third loop, a fifth pass voltage to the at least one second word line;
• and
• applying, during a second stage of the third loop, a sixth pass voltage to the at least one second word line,
• wherein the second loop is after the first loop, the third loop is after the second loop, the second program voltage is higher than the first program voltage, and the third program voltage is higher than the second program voltage, and
• wherein the third pass voltage is lower than the first pass voltage, and the fifth pass voltage is higher than the third pass voltage;
• and
• a memory controller coupled to the memory device and configured to control the memory device.