Compute in memory (cim) module

A Compute In Memory (CIM) module comprising:

• a first transistor array in which a plurality of unit transistors is arranged;
• and
• a second transistor array configured to perform multiplication and accumulation (MAC) computation,
• wherein the first transistor array includes:
• a first row digital-to-analog converter (DAC) configured to apply a voltage corresponding to a first initial input voltage value used in the MAC computation to drain electrodes of the unit transistors arranged in a first row of the first transistor array;
• a first column DAC configured to apply a voltage corresponding to a change amount of a first error for the MAC computation with respect to a first current value formed as a result of performing the MAC computation to gate electrodes of the unit transistors arranged in a first column of the first transistor array;
• and
• a first analog-to-digital converter (ADC) configured to output a digital signal corresponding to a current flowing into source electrodes of the unit transistors arranged in the first column.

A Compute In Memory (CIM) module comprising:

• a transistor array computer including at least one transistor and at least one resistive random access memory (ReRAM) for each unit cell;
• a buffer;
• and
• a weight gradient computer in which unit transistors are arranged in a plurality of rows and a plurality of columns,
• wherein the weight gradient computer includes:
• a plurality of bit-lines configured to transmit a signal corresponding to an initial input voltage value used in multiplication and accumulation (MAC) computation to first electrodes of unit transistors arranged in each row;
• a plurality of word-lines configured to transmit, to second electrodes of unit transistors arranged in each column, a signal corresponding to a change amount in error for the MAC computation with respect to a current value formed as a result of performing the MAC computation;
• and
• a plurality of source lines configured to transmit a signal corresponding to a current flowing into third electrodes of unit transistors arranged in each column.