Systems and methods for multi-pumping memory with flip-flop interface

A memory circuit, comprising:

• a memory array comprising a plurality of memory cells;
• a first latch coupled to a pin and a control line carrying a clock signal;
• and
• a second latch coupled to the first latch, the control line, and the memory array,
• wherein the first latch is configured to propagate signals when the clock signal is low and stop propagation of the signals when the clock signal is high, and
• wherein the second latch is configured to propagate signals when the clock signal is high and stop propagation of the signals when the clock signal is low.

A method for operating a memory device having a memory array comprising a plurality of memory cells, the method comprising:

• sending a clock signal in a low state or a high state to a low-through latch (LL) and a high-through latch (HL) via a control line, wherein the LL is coupled to a pin and the control line, and the HL is coupled to the LL, the control line, and the memory array;
• during the high state of the clock signal, propagating signals via the HL and stopping propagation of signals via the LL;
• and
• during the low state of the clock signal, propagating signals via the LL and stopping propagation of signals via the HL.