Area and power efficient partial word feature in embedded memories

Abstract

A static random-access memory (SRAM) device with enhanced flexibility and power efficiency includes two memory cores with different bit widths and a control section that receives a partial word signal. This signal allows independent control of each memory core, enabling or disabling them selectively. The SRAM device further includes a decoder circuit and multiple word line drivers, which can be independently enabled or disabled for each memory core based on the partial word signal. The word line drivers are organized into two sets, each coupled to the word lines of a respective memory core. Power control circuits selectively provide power to each set of drivers according to the partial word signal. This architecture allows for more granular control over memory access and power consumption, potentially improving the device's overall efficiency and performance in applications requiring variable memory access patterns.

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