Semiconductor device

A semiconductor device comprising:

• a substrate comprising a first surface and a second surface, which are opposite to each other;
• a plurality of unit static random access memory (SRAM) cells arranged in a matrix along first and second directions crossing each other, on the first surface;
• a first word line extending along the first direction on the first surface;
• and
• a second word line extending along the first direction on the second surface,
• wherein the plurality of unit SRAM cells comprise first unit SRAM cells arranged in a first row and second unit SRAM cells arranged in a second row, each of the first and second rows extending along the first direction,
• wherein the first word line is commonly connected to the first unit SRAM cells of the first row, and
• wherein the second word line is commonly connected to the second unit SRAM cells of the second row.

A semiconductor device comprising:

• first and second cells adjacent to each other along a first direction;
• a substrate comprising a first surface and a second surface, which are opposite to each other;
• first to fourth active patterns, which are sequentially arranged along a second direction crossing the first direction, each of the first to fourth active patterns extending along the first direction on the first surface;
• a first gate structure, which extends along the second direction across the first active pattern, in the first cell;
• a second gate structure, which extends along the second direction across the third and fourth active patterns, in the first cell;
• a third gate structure, which extends along the second direction across the first and second active patterns, in the first cell;
• a fourth gate structure, which extends along the second direction across the fourth active pattern, in the first cell;
• a first source/drain contact, which connects the first active pattern with the second active pattern and the second gate structure, between the first gate structure and the third gate structure, and between the second gate structure and the third gate structure;
• a second source/drain contact, which connects the third active pattern with the fourth active pattern and the third gate structure, between the second gate structure and the third gate structure, and between the second gate structure and the fourth gate structure;
• a fifth gate structure, which extends along the second direction across the first active pattern, in the second cell;
• a sixth gate structure, which extends along the second direction across the third and fourth active patterns, in the second cell;
• a seventh gate structure, which extends along the second direction across the first and second active patterns, in the second cell;
• an eighth gate structure, which extends along the second direction across the fourth active pattern, in the second cell;
• a third source/drain contact, which connects the first active pattern with the second active pattern and the sixth gate structure, between the fifth gate structure and the seventh gate structure, and between the sixth gate structure and the seventh gate structure;
• a fourth source/drain contact, which connects the third active pattern with the fourth active pattern and the seventh gate structure, between the sixth gate structure and the seventh gate structure, and between the sixth gate structure and the eighth gate structure;
• a first frontside wiring pattern, which extends along the second direction and is connected to the first and fourth gate structures, on the first surface;
• and
• a first backside wiring pattern, which extends along the second direction and is connected to the fifth and eighth gate structures, on the second surface.