US 2026/0088076 A1 · ADJUSTING TRAINING DELAYS IN SDRAM

Abstract

Embodiments herein describe techniques for providing individual clock delay values to each rank coupled to a memory controller. A register (e.g., a mode register (MR)) can store an offset delay for each of the ranks relative to a minimum clock delay of the ranks. For example, the memory controller can calculate the clock delay for each rank and then find the difference (or delta) between the individual clock delay values and the minimum clock delay value. The memory controller can write these difference/deltas to the registers for the ranks. The ranks can then use the value stored in their respective registers to further delay a received clock signal that has already been delay by the minimum clock delay value.

Claims20

Dependent claims

A memory controller, comprising:

a clock source configured to output a clock signal to a plurality of ranks;
and
a level trainer comprising circuitry configured to:
perform level training to generate a first clock delay for a first rank of the plurality of ranks,
perform level training to generate a second clock delay for a second rank of the plurality of ranks, wherein the first clock delay is less than the second clock delay,
write a delta between the second clock delay and the first clock delay in a register in the second rank, and
transmit the clock signal to both the first and second ranks that is delayed by the first clock delay, wherein the second rank is configured to further delay the clock signal using the delta written in the register.

4 more elements

Dependencies are inferred from the claim text.

Adjusting training delays in sdram

Life of this patent

Adjusting training delays in sdram

Life of this patent

Abstract

Claims20