Control Method and Apparatus for Memory, and Electronic Device

An electronic apparatus comprising:

• a memory comprising:
• a bit line;
• a plurality of transistors coupled to the bit line;
• a plurality of word lines;
• a memory cell array comprising memory cells, wherein the memory cells located in a same column in the memory cell array are coupled to a same transistor or the transistors and a same word line of the word lines;
• and
• a plurality of plate lines, wherein the memory cells located in a same row in the memory cell array are coupled to a selected plate line of the plate lines;
• and
• control apparatus coupled to the memory and comprising:
• a first control circuit configured to activate, in a first sub-phase of an active phase of a target memory cell and through an unselected word line, a first transistor of the transistors and coupled to the unselected word line, apply a first voltage V1 to the bit line, and apply a second voltage V2 to an unselected plate line;
• and
• a second control circuit, configured to activate, in a second sub-phase of the active phase, through a selected word line, a second transistor of the transistors and coupled to the selected word line, apply a third voltage V3 to the bit line, and apply a fourth voltage V4 to the selected plate line, wherein word line voltage Vw=|V4−V3|, |V4−V1|<½Vw, and |V3−V2|<½Vw.