Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell including a semiconductor layer, a gate electrode layer, and a gate insulating layer containing a ferroelectric and provided between the semiconductor layer and the gate electrode layer;
• a first wiring and a second wiring electrically connected to the semiconductor layer;
• and
• a control circuit configured to control the memory cell,
• wherein the control circuit is configured to execute a first write operation to the memory cell, and in the first write operation, a first voltage pulse having a first voltage with a first polarity and a first pulse width is applied between the gate electrode layer and at least one of the first wiring and the second wiring,
• the control circuit is configured to execute an erase operation to the memory cell, and in the erase operation, a second voltage pulse having a second voltage with a second polarity opposite to the first polarity and a second pulse width is applied between the gate electrode layer and at least one of the first wiring and the second wiring,
• the control circuit is configured to execute a second write operation to the memory cell, and in the second write operation, a third voltage pulse having a third voltage with the first polarity having a smaller absolute value than an absolute value of the first voltage and a third pulse width is applied between the gate electrode layer and at least one of the first wiring and the second wiring,
• the control circuit is configured to determine whether or not number of times of execution of the second write operation to the memory cell has reached a predetermined first number of times, and
• the control circuit is configured to execute a first operation to the memory cell when it is determined that the number of times of execution has reached the predetermined first number of times, and
• in the first operation, a fourth voltage pulse having a fourth voltage with the first polarity having a larger absolute value than the absolute value of the third voltage and a fourth pulse width and a fifth voltage pulse having a fifth voltage with the second polarity having a larger absolute value than the absolute value of the third voltage and a fifth pulse width are applied between the gate electrode layer and at least one of the first wiring and the second wiring, and the fifth voltage pulse is applied consecutively after the fourth voltage pulse is applied.

A semiconductor memory device comprising:

• a memory cell array including
• a first semiconductor layer extending in a first direction,
• a plurality of gate electrode layers stacked in the first direction,
• a first wiring electrically connected to the first semiconductor layer,
• a second wiring electrically connected to the first semiconductor layer, and
• a plurality of first memory cells, each of the first memory cells including the first semiconductor layer, one gate electrode layer of the gate electrode layers, and a gate insulating layer containing a ferroelectric and provided between the first semiconductor layer and the one gate electrode layer;
• and
• a control circuit configured to control the first memory cells,
• wherein the control circuit is configured to execute a first write operation to one first memory cell selected from the first memory cells, and in the first write operation, a first voltage pulse having a first voltage with a first polarity and a first pulse width is applied between the one gate electrode layer of the one first memory cell and at least one of the first wiring and the second wiring,
• the control circuit is configured to execute an erase operation to the one first memory cell, and in the erase operation, a second voltage pulse having a second voltage with a second polarity opposite to the first polarity and a second pulse width is applied between the one gate electrode layer of the one first memory cell and at least one of the first wiring and the second wiring,
• the control circuit is configured to execute a second write operation to the one first memory cell, and in the second write operation, a third voltage pulse having a third voltage with the first polarity having a smaller absolute value than an absolute value of the first voltage and a third pulse width is applied between the one gate electrode layer of the one first memory cell and at least one of the first wiring and the second wiring, and
• the control circuit is configured to execute a first operation to the one first memory cell before the second write operation, the first operation is consecutive with the second write operation, and
• in the first operation, a fourth voltage pulse having a fourth voltage with the first polarity having a larger absolute value than the absolute value of the third voltage and a fourth pulse width and a fifth voltage pulse having a fifth voltage with the second polarity having a larger absolute value than the absolute value of the third voltage and a fifth pulse width are applied between the one gate electrode layer of the one first memory cell and at least one of the first wiring and the second wiring, and the fifth voltage pulse is applied consecutively after the fourth voltage pulse is applied.

A semiconductor memory device comprising:

• a memory cell array including
• a first semiconductor layer extending in a first direction,
• a second semiconductor layer extending in the first direction,
• a plurality of gate electrode layers stacked in the first direction,
• a first wiring electrically connected to the first semiconductor layer and the second semiconductor layer,
• a second wiring electrically connected to the first semiconductor layer,
• a third wiring electrically connected to the second semiconductor layer,
• a plurality of first memory cells, each of the first memory cells including the first semiconductor layer, one gate electrode layer of the gate electrode layers, and a gate insulating layer containing a ferroelectric and provided between the first semiconductor layer and the one gate electrode layer, and
• a plurality of second memory cells, each of the second memory cells including the second semiconductor layer, one gate electrode layer of the gate electrode layers, and a gate insulating layer containing a ferroelectric and provided between the second semiconductor layer and the one gate electrode layer;
• and
• a control circuit configured to control the first memory cells and the second memory cells,
• wherein the control circuit is configured to execute a first write operation to any one memory cell of the first memory cells and the second memory cells, and in the first write operation, a first voltage pulse having a first voltage with a first polarity and a first pulse width is applied between one gate electrode layer of the one memory cell and at least one of the first wiring and the second wiring when the one memory cell is one of the first memory cells, or in the first write operation, the first voltage pulse having the first voltage with the first polarity and the first pulse width is applied between one gate electrode layer of the one memory cell and at least one of the first wiring and the third wiring when the one memory cell is one of the second memory cells,
• the control circuit is configured to execute an erase operation to the first memory cells and the second memory cells, and in the erase operation, a second voltage pulse having a second voltage with a second polarity opposite to the first polarity and a second pulse width is applied between gate electrode layers and the first wiring,
• the control circuit is configured to execute a second write operation to the one memory cell, and in the second write operation, a third voltage pulse having a third voltage with the first polarity having a smaller absolute value than an absolute value of the first voltage and a third pulse width is applied between the one gate electrode layer of the one memory cell and at least one of the first wiring and the second wiring when the one memory cell is one of the first memory cells, or in the second write operation, the third voltage pulse having the third voltage with the first polarity having a smaller absolute value than the absolute value of the first voltage and the third pulse width is applied between the one gate electrode layer of the one memory cell and at least one of the first wiring and the third wiring when the one memory cell is one of the second memory cells,
• the control circuit is configured to determine whether or not number of times of execution of the second write operation to each of the first memory cells and the second memory cells has reached a predetermined first number of times, and
• the control circuit is configured to execute a first operation to the first memory cells and the second memory cells when it is determined that the number of times of execution to any of the first memory cells and the second memory cells has reached the predetermined first number of times, and
• in the first operation, a fourth voltage pulse having a fourth voltage with the first polarity having a larger absolute value than the absolute value of the third voltage and a fourth pulse width and a fifth voltage pulse having a fifth voltage with the second polarity having a larger absolute value than the absolute value of the third voltage and a fifth pulse width are applied between the gate electrode layers and the first wiring, and the fifth voltage pulse is applied consecutively after the fourth voltage pulse is applied.

A semiconductor memory device comprising:

• a memory cell including a semiconductor layer, a gate electrode layer, a gate insulating layer provided between the semiconductor layer and the gate electrode layer, a first conductive layer electrically connected to the semiconductor layer, a second conductive layer, and a capacitor insulating layer containing a ferroelectric and provided between the first conductive layer and the second conductive layer;
• a first wiring electrically connected to the first conductive layer via the semiconductor layer and a second wiring electrically connected to the second conductive layer;
• and
• a control circuit configured to control the memory cell,
• wherein the control circuit is configured to execute a first write operation to the memory cell, and in the first write operation, a first voltage pulse having a first voltage with a first polarity and a first pulse width is applied between the first wiring and the second wiring,
• the control circuit is configured to execute an erase operation to the memory cell, and in the erase operation, a second voltage pulse having a second voltage with a second polarity opposite to the first polarity and a second pulse width is applied between the first wiring and the second wiring,
• the control circuit is configured to execute a second write operation to the memory cell, and in the second write operation, a third voltage pulse having a third voltage with the first polarity having a smaller absolute value than an absolute value of the first voltage and a third pulse width is applied between the first wiring and the second wiring, and
• the control circuit is configured to execute a first operation to the memory cell before the second write operation, the first operation is consecutive with the second write operation, and
• in the first operation, a fourth voltage pulse having a fourth voltage with the first polarity having a larger absolute value than the absolute value of the third voltage and a fourth pulse width and a fifth voltage pulse having a fifth voltage with the second polarity having a larger absolute value than the absolute value of the third voltage and a fifth pulse width are applied between the first wiring and the second wiring, and the fifth voltage pulse is applied consecutively after the fourth voltage pulse is applied.

A semiconductor memory device comprising:

• a memory cell including a semiconductor layer, a gate electrode layer, a gate insulating layer provided between the semiconductor layer and the gate electrode layer, a first conductive layer electrically connected to the semiconductor layer, a second conductive layer, and a capacitor insulating layer containing a ferroelectric and provided between the first conductive layer and the second conductive layer;
• a first wiring electrically connected to the first conductive layer via the semiconductor layer and a second wiring electrically connected to the second conductive layer;
• and
• a control circuit configured to control the memory cell,
• wherein the control circuit is configured to execute a first write operation to the memory cell, and in the first write operation, a first voltage pulse having a first voltage with a first polarity and a first pulse width is applied between the first wiring and the second wiring,
• the control circuit is configured to execute an erase operation to the memory cell, and in the erase operation, a second voltage pulse having a second voltage with a second polarity opposite to the first polarity and a second pulse width is applied between the first wiring and the second wiring,
• the control circuit is configured to execute a second write operation to the memory cell, and in the second write operation, a third voltage pulse having a third voltage with the first polarity having a smaller absolute value than an absolute value of the first voltage and a third pulse width is applied between the first wiring and the second wiring,
• the control circuit is configured to determine whether or not number of times of execution of the second write operation to the memory cell has reached a predetermined first number of times, and
• the control circuit is configured to execute a first operation to the memory cell when it is determined that the number of times of execution has reached the predetermined first number of times, and
• in the first operation, a fourth voltage pulse having a fourth voltage with the first polarity having a larger absolute value than the absolute value of the third voltage and a fourth pulse width and a fifth voltage pulse having a fifth voltage with the second polarity having a larger absolute value than the absolute value of the third voltage and a fifth pulse width are applied between the first wiring and the second wiring, and the fifth voltage pulse is applied consecutively after the fourth voltage pulse is applied.