Semiconductor memory device

A semiconductor memory device comprising:

• a first chip which comprises a plurality of memory blocks that are arranged in a first direction and extend in a second direction intersecting the first direction;
• and
• a second chip which is bonded to the first chip via a bonding electrode, wherein
• the plurality of memory blocks each comprise:
• a plurality of word line conductive layers stacked in a stacking direction;
• a semiconductor column which extends in the stacking direction and faces the plurality of word line conductive layers;
• and
• an electric charge accumulating film provided between the plurality of word line conductive layers and the semiconductor column,
• the second chip comprises:
• a semiconductor substrate;
• a plurality of transistor groups which are provided on the semiconductor substrate correspondingly to the plurality of memory blocks, are arranged in the first direction, and each include a plurality of transistors arranged in the second direction;
• a block decoder which is provided on the semiconductor substrate, and decodes a block address to select one of the plurality of memory blocks;
• a first wiring layer provided between the semiconductor substrate and the first chip;
• and
• a second wiring layer provided between the first wiring layer and the first chip,
• the second wiring layer comprises a plurality of word line voltage supply line groups and a plurality of block select line groups that are arranged alternately in the second direction,
• the plurality of word line voltage supply line groups each comprise a plurality of word line voltage supply lines which extend in the first direction and are arranged in the second direction,
• the plurality of word line voltage supply lines are each commonly electrically connected to corresponding ones of the plurality of word line conductive layers included in each of the plurality of memory blocks, via a corresponding one of the plurality of transistors included in each of the plurality of transistor groups,
• the plurality of block select line groups each comprise a plurality of block select lines which extend in the first direction from a position in the first direction corresponding to the block decoder to a position in the first direction corresponding to a corresponding one of the plurality of transistor groups, and are arranged in the second direction,
• the plurality of block select lines are each commonly electrically connected to gate electrodes of n transistors included in a corresponding one of the plurality of transistor groups,
• the plurality of block select line groups each include a first block select line and a second block select line,
• the first block select line, which is a first block select line counting from one side in the second direction, of the plurality of block select lines, comprises a first bent portion where the first block select line is bent in a direction of getting further away from the word line voltage supply line adjacent in the second direction,
• the second block select line comprises a first connecting portion which is electrically connected at its end portion in the first direction to the first wiring layer, and
• positions in the first direction of the first bent portions in each of the plurality of block select line groups differ from each other.