US 2026/0087584 A1 · Tiled Minimal Latency Content Update

Abstract

Systems, methods, and devices are provided to reduce latency in displaying image data on an electronic display. This may include instructing image processing circuitry to read a first tile of image data from a first framebuffer, determining whether the first framebuffer or a second framebuffer has a more recent second tile after the first tile and, based on whether the first framebuffer or the second framebuffer has the more recent second tile, instructing the image processing circuitry to read the second tile from the first framebuffer or the second framebuffer that has the more recent second tile.

Claims22

Dependent claims

An article of manufacture comprising tangible, non-transitory, machine-readable media comprising instructions that, when executed by a data processing system, cause the data processing system to carry out operations comprising:

instructing image processing circuitry to read a first tile of image data from a first framebuffer;
determining whether the first framebuffer or a second framebuffer has a more recent second tile after the first tile;
and
based on whether the first framebuffer or the second framebuffer has the more recent second tile, instructing the image processing circuitry to read the second tile from the first framebuffer or the second framebuffer that has the more recent second tile.

1 more element

Dependencies are inferred from the claim text.

Tiled Minimal Latency Content Update

Life of this patent

Tiled Minimal Latency Content Update

Life of this patent

Abstract

Claims22