Graphics Processor Power Management Controlled by Distribution Hardware

A method, comprising:

• storing graphics work, by respective distributed work queue circuitry of first and second graphics processor sub-units of a graphics processor;
• executing, by respective shader circuitry of the first and second graphics processor sub-units, instructions specified by stored graphics work in the corresponding sub-unit's distributed work queue circuitry;
• access, by work control circuitry, graphics work in multiple primary queues;
• distribute, by the work control circuitry, portions of respective sets of graphics work accessed from the multiple primary queues to the first and second graphics processor sub-units for execution;
• tracking, by the work control circuitry, status of assigned sets of graphics work;
• and
• communicating, by the work control circuitry, with power control circuitry to control power state of portions of the graphics processor based on:
• status of multiple primary queues;
• and
• status of assigned and tracked sets of graphics work.

A non-transitory computer-readable medium having instructions of a hardware description programming language stored thereon that, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents a hardware circuit that includes:

• a graphics processor that includes:
• at least first and second graphics processor sub-units that respectively include:
• distributed work queue circuitry configured to store graphics work;
• and
• shader circuitry configured to execute instructions specified by stored graphics work in the sub-unit's distributed work queue circuitry;
• work control circuitry that includes:
• queue access circuitry configured to access graphics work in multiple primary queues;
• distribution circuitry configured to assign portions of respective sets of graphics work accessed from the multiple primary queues to the first and second graphics processor sub-units for execution;
• tracking circuitry configured to track status of assigned sets of graphics work;
• and
• power control circuitry, wherein the work control circuitry is configured to communicate with the power control circuitry to control power state of portions of the graphics processor based on:
• status of multiple primary queues;
• and
• status of assigned sets of graphics work tracked by the tracking circuitry.