Signoff-accurate vlsi gate sizing for simultaneous timing and power optimization using large language models

A system for performing very large scale integration (VLSI) gate sizing for power, performance, and area (PPA) optimization, comprising:

• one or more processors;
• and
• a non-transitory computer-readable medium having processor-executable instructions stored thereon, wherein the processor-executable instructions, when executed by the one or more processors, facilitate:
• obtaining initial data structures associated with a circuit pathway indicating a pathway for a signal to propagate from a start point, through a plurality of hardware gates, to an end point;
• generating a plurality of input strings for the plurality of hardware gates using the initial data structures;
• using a first embedding generator to generate first embeddings for the plurality of input strings;
• and
• generating output strings for the plurality of hardware gates based on processing the first embeddings associated with the plurality of input strings using a large language model (LLM), wherein the output strings indicate optimized library cells (LibCells) for the plurality of hardware gates from a LibCell database.

A non-transitory computer-readable medium having processor-executable instructions stored thereon, wherein the processor-executable instructions, when executed, facilitate:

• obtaining initial data structures associated with a circuit pathway indicating a pathway for a signal to propagate from a start point, through a plurality of hardware gates, to an end point;
• generating a plurality of input strings for the plurality of hardware gates using the initial data structures;
• using a first embedding generator to generate first embeddings for the plurality of input strings;
• and
• generating output strings for the plurality of hardware gates based on processing the first embeddings associated with the plurality of input strings using a large language model (LLM), wherein the output strings indicate optimized library cells (LibCells) for the plurality of hardware gates from a LibCell database.