Systems and methods for identifying and modifying unused logic in circuit designs

A method for circuit design, comprising:

• obtaining Extracted Timing Model (ETM) information for a plurality of design blocks of a circuit design, the ETM information indicating hierarchical timing information for the plurality of design blocks;
• identifying floating port information for at least one design block of the plurality of design block;
• modifying the ETM information based on the identified floating port information;
• obtaining top level register transfer level (RTL) information for the plurality of design blocks, the RTL information indicating top level RTL designs for the plurality of design blocks;
• determining an engineering change order (ECO) for the at least one design block based on the identified floating port information for the at least one design block;
• updating netlist information for the at least one design block based on the ECO;
• performing top level synthesis for the circuit design based on the top level RTL information and the modified ETM information to generate top level synthesis information;
• performing a logical equivalence check (LEC) between the top level RTL information and the updated netlist information to determine LEC update data;
• performing a LEC on the top level synthesis information based on the LEC update data;
• validating the updated netlist information based on performance of the LEC on the top level synthesis information;
• and
• outputting a validated netlist file based on validation of the updated netlist information, the validated netlist file generated based on the identified floating port information and including modified logic associated with the ECO.

A hard macro of an integrated circuit comprising:

• a first plurality of input ports coupled to one or more neighboring hard macros of the integrated circuit;
• a first plurality of output ports coupled to the one or more neighboring hard macros, the first plurality of input port and the first plurality of output ports coupled to a supply voltage of the integrated circuit;
• and
• one or more floating input ports or floating output ports that are not connected to any other hard macros of the integrated circuit, the one or more floating input ports or floating output ports are not coupled to any supply voltage of the integrated circuit.