Rate Control for Matrix Accelerator Hardware

A method, comprising:

• executing, by a processor of a computing device, a first matrix multiply instruction and a second matrix multiply instruction included in an execution thread;
• generating, by the computing device, a first set of operations, including multiple dot product and multiple accumulate operations, for the first matrix multiply instruction;
• generating, by the computing device, a second set of operations, including multiple dot product and multiple accumulate operations, for the second matrix multiply instruction;
• performing, by matrix acceleration hardware of the computing device, the first set of operations at a first execution rate;
• and
• performing, by the matrix acceleration hardware, the second set of operations at a second, different execution rate.

A non-transitory computer-readable medium having instructions of a hardware description programming language stored thereon that, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents a hardware circuit that includes:

• processor circuitry configured to execute a first matrix multiply instruction and a second matrix multiply instruction included in an execution thread;
• control circuitry configured to:
• generate:
• a first set of operations, including multiple dot product and multiple accumulate operations, for the first matrix multiply instruction;
• and
• a second set of operations, including multiple dot product and multiple accumulate operations, for the second matrix multiply instruction;
• and
• specify a first execution rate for the first set of operations and a second, different execution rate for the second set of operations;
• matrix acceleration circuitry configured to:
• perform the first set of operations at the first execution rate;
• and
• perform the second set of operations at the second execution rate.