DRAM with Single Clock for Command/Address and Write Data

A method, comprising:

• receiving, at a dynamic random-access memory (DRAM) device from a memory interface circuit, a first differential clock signal at a first pair of pins of an external interface of the DRAM device, the DRAM device including a set of DRAM cells, a first command and address bus that is 4 bits wide, and a first data bus that is thirty-two bits wide;
• indicating, by the DRAM device based on the first differential clock signal, validity of information on the first command and address bus;
• and
• indicating, by the DRAM device based on the first differential clock signal, validity of write data for an entirety of the first data bus, the first differential clock signal being distributed within the DRAM device via a first clock distribution circuit coupled to the first pair of pins.

An apparatus, comprising:

• a computer system formed on one or more co-packaged integrated circuits, the computer system including:
• a network circuit;
• a plurality of agent circuits configured to communicate via the network circuit, the plurality of agent circuits including a plurality of processor circuits and a memory controller circuit that includes a memory interface circuit;
• a dynamic random-access memory (DRAM) device coupled to the computer system via the memory interface circuit, wherein the DRAM device includes:
• a set of DRAM cells, including a first portion of DRAM cells;
• an external interface that includes a first pair of pins for a clock interface, four pins for a first command and address bus coupled to the first portion of DRAM cells, and thirty two pins for a first data bus coupled to the first portion of DRAM cells;
• the first command and address bus;
• the first data bus;
• a first clock distribution circuit coupled to the first pair of pins;
• and
• wherein the DRAM device is configured to:
• receive, from the memory interface circuit at the first pair of pins, a first differential clock signal;
• drive, by the first clock distribution circuit based on the first differential clock signal, an indication of validity of:
• information on the first command and address bus;
• and
• thirty-two bits of write data being conveyed to the DRAM device via the first data bus.