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US 2026/0086948 A1Published application
Unloaded cache bypass
AssigneeMicron Technology, Inc.
InventorEmanuele Confalonieri
Life of this patent
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Abstract
Systems, apparatuses, and methods related to a memory controller for unloaded cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache. The cache can include a cache sequence controller configured to determine a quantity of a pending cache look-up operations, determine the quantity satisfies an unloaded bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.
Claims20
A system, comprising:
- a memory device;
- and
- a memory controller coupled to the memory device and comprising:
- a cache including a metric logic configured to track a quantity of pending cache look-up operations in a queue of the cache;
- and
- a cache sequence controller coupled to the cache and configured to:
- compare the quantity of pending cache look-up operations to a threshold quantity responsive to receiving a read request from a host, wherein the threshold is varied based on a cache hit rate of cache look-up operations;
- and
- cause performance of a bypass read operation that bypasses the cache and accesses the memory device responsive to determining the quantity is less than or equal to the threshold.
6 more elements
A method, comprising:
- determining, by a memory controller coupled to a memory device, a quantity of pending cache look-up operations in a queue associated with a cache responsive to receiving a host access request;
- determining the quantity of pending cache look-up operations is less than or equal to a threshold that is variable based on a cache hit rate of cache look-up operations;
- and
- responsive to determining the quantity of pending cache look-up operations is less than or equal to the threshold:
- causing performance of a bypass read operation that bypasses the cache and accesses the memory device;
- and
- causing performance of a cache look-up operation substantially contemporaneously with the performance of the bypass read operation.
4 more elements
An apparatus, comprising:
- a memory device;
- and
- a memory controller coupled to the memory device and comprising:
- a cache including a metric logic configured to track a quantity of pending cache look-up operations in a queue of the cache;
- and
- a cache sequence controller coupled to the cache and configured to:
- responsive to receiving a host read request:
- determine that the quantity of pending cache look-up operations satisfies a variable unloaded bypass threshold, wherein the variable unloaded bypass threshold is varied based on a cache hit rate of cache look-up operations;
- cause performance of a cache look-up operation;
- and
- in parallel with performance of the cache look-up operation, cause initiation of a bypass read operation that bypasses the cache and accesses the memory device to read data corresponding to the host read request from the memory device.
8 more elements
Dependencies are inferred from the claim text.