Disaggregated Host Memory Buffer Implemented via Random Access Memory Connected via Computer Express Link Fabric

A system, comprising:

• a compute express link fabric;
• a plurality of memory devices having random access memory cells, each of the plurality of memory devices connected to the compute express link fabric via a separate compute express link connection;
• a memory bus;
• a main memory;
• at least one processing device connected to the main memory via the memory bus, and connected to the compute express link fabric;
• a peripheral bus;
• and
• a plurality of memory sub-systems connected to the at least one processing device via the peripheral bus;
• wherein a plurality of portions of the random access memory cells in the plurality of memory devices are allocated respectively as a plurality of host memory buffers for the plurality of memory sub-systems, wherein at least one of the plurality of host memory buffers is disaggregated on more than one of the plurality of memory devices.

A memory sub-system, comprising:

• a host interface configured to operate on a computer bus;
• non-volatile memory cells configured to provide a persistent storage space addressable over the host interface via logical block addressing addresses;
• and
• at least one processing device configured to:
• process storage access requests received over the host interface;
• allocate a portion of random access memory over the host interface and a compute express link fabric, wherein the portion of the random access memory is disaggregated on more than one memory device connected to the compute express link fabric;
• buffer at least a portion of a logical to physical translation table in the portion of random access memory;
• and
• convert, using the portion of the logical to physical translation table buffered in the portion of the random access memory, the logical block addressing addresses to physical addresses of the non-volatile memory cells in processing of the storage access requests.