Memory system

1616 The memory system according to claim 11, wherein the controller is further configured to:

• after transmitting the address, transmit a first portion of dummy data to the memory device via the first signal line while the data strobe signal is maintained at a low level;
• and
• after transmitting the first portion of the dummy data, transmit a second portion of the dummy data to the memory device via the first signal line in synchronization with the toggling of the data strobe signal for the first period.

The memory system according to claim 16, wherein

• the dummy data includes first dummy data and second dummy data following the first dummy data, and
• the first dummy data is data in which all bits have a first value, and the second dummy data is data in which all bits have a second value different from the first value.

The memory system according to claim 16, wherein

• the dummy data includes first dummy data and second dummy data following the first dummy data, and
• the first dummy data is data in which even-numbered bits have a first value and odd-numbered bits have a second value different from the first value, and the second dummy data is data in which even-numbered bits have the second value and odd-numbered bits have the first value.

The memory system according to claim 16, wherein the controller is configured to:

• transmit the second portion of the dummy data in synchronization with rising and falling edges of the data strobe signal;
• and
• transmit the first data in synchronization with the rising and falling edges of the data strobe signal.