Two-Activate Timing Window for DRAM

A method, comprising:

• generating, by a memory interface circuit of a computer system, a first activate command to a first row in a first bank group of a dual data rate (DDR) dynamic random-access memory (DRAM) device;
• beginning, by the memory interface circuit based on generation of the first activate command, a current two-activate timing window having a first time period;
• preventing, by the memory interface circuit during the current two-activate timing window, generation of more than one additional activate command;
• and
• beginning, by the memory interface circuit based on expiration of the current two-activate timing window, a new current two-activate timing window.

A computer system, comprising:

• a network circuit;
• a plurality of agent circuits configured to communicate with one another via the network circuit, wherein the plurality of agent circuits includes a plurality of processor circuits and a memory controller circuit;
• and
• a memory system coupled to a memory interface circuit of the memory controller circuit, wherein the memory system includes one or more dual data rate (DDR) dynamic-random access memory (DRAM) devices that have different bank groups of DRAM cells;
• and
• wherein a given DRAM device is configured to activate a respective row of DRAM cells in response to receiving an activate command from the memory interface circuit;
• and
• wherein the memory interface circuit is configured to ensure that no more than two activate commands are generated to the DRAM device within a specified time period corresponding to a two-activate timing window.