Power-efficient clock generator with integrated clock gating logic

A clock generator with built-in clock gating logic, comprising:

• a plurality of sub-dividers, receiving and dividing an input clock of the clock generator to generate a plurality of divided clocks;
• a plurality of multiplexers, receiving a control signal and coupled to the sub-dividers to receive the divided clocks, outputting a selected clock according to the control signal as an output clock of the clock generator, wherein each multiplexer is arranged to receive two input clocks and generate one output clock according to a select signal, and each multiplexer outputs internal states indicating the input clocks being active or inactive, wherein the two input clocks of each multiplexer are selecting from the input clock of the clock generator, the divided clocks output from the sub-dividers, and the output clocks of other multiplexers;
• and
• a clock selection controlling clock gate logic, receiving the internal states from the multiplexers and generating selection signals for the sub-dividers according to the internal states;
• wherein each of the sub-dividers is ungated or gated depending on the corresponding selection signal output from the clock selection controlling clock gate logic.