US 2026/0086597 A1 · SYSTEMS AND METHODS FOR REDUCING POWER LEAKAGE IN A SYSTEM-ON-A-CHIP (SOC)

Abstract

Systems and methods are provided for reducing power consumption in an SoC by reducing the clock frequency of a cluster of processing cores or by reducing both the clock frequency and the supply voltage of the cluster when the cluster is in clock gating mode. With existing clock gating processes used in SoCs, if a cluster is in clock gating mode, the clock is still running at the same speed as when ungated, which results in significant power leakage. If the clock is running at a higher speed when the cluster is in clock gating mode, more power leakage will occur than if the clock is running at a lower speed when the cluster is in clock gating mode. By reducing the clock frequency of the cluster when it is in clock gating mode, a substantial reduction in power leakage can be realized.

Claims20

Dependent claims

A method for reducing power leakage in a system-on-a-chip (SoC), the method comprising:

determining when at least a first cluster of processing cores has entered a cluster clock gating state;
and
in response to determining that the first cluster has entered the cluster clock gating state, reducing a clock frequency used by the processing cores of the first cluster from a first clock frequency to a second clock frequency, the second clock frequency being less than the first clock frequency.

A computer program for controlling a power management system in a system-on-a-chip (SoC) to perform power management, the computer program being embodied on a non-transitory computer readable medium and comprising computer instructions for execution by one or more processors, the computer instructions comprising:

a first set of computer instructions for determining when at least a first cluster of processing cores has entered a cluster clock gating state;
and
a second set of computer instructions for, in response to determining that the first cluster has entered the cluster clock gating state, reducing a clock frequency used by the processing cores of the first cluster from a first clock frequency to a second clock frequency, the second clock frequency being less than the first clock frequency.

Dependencies are inferred from the claim text.

Systems and methods for reducing power leakage in a system-on-a-chip (soc)

Life of this patent

Systems and methods for reducing power leakage in a system-on-a-chip (soc)

Life of this patent

Abstract

Claims20