Chiplet testing with lower speed interface

Abstract

Embodiments herein relate to testing chiplets during the manufacturing process. In one aspect, an on-chiplet interface is provided which allows testing of inter-chiplet communications of a chiplet on a package substrate without requiring the use of another chiplet. The interface communicates with an external Field-Programmable Gate Array (FPGA) on the package substrate at a reduced frequency compared to a frequency of the inter-chiplet communications. The FPGA can in turn communicate with a workstation to receive instructions and provide test results. The FPGA sends test pattern signals to, and evaluates corresponding responses from, circuitry of the chiplet which implements an inter-chiplet communication standard such as the Universal Chiplet Interconnect Express (UCIe) standard. In another aspect, the physical layer (PHY) circuits of two chiplet are tested with respective FPGAs.

Dependencies are inferred from the claim text.