Signaling that includes inversion information and link parity information

A memory system, comprising:

• one or more controllers configured to:
• obtain, from a host system and via a first bus, a message comprising data, an inversion configuration, and link parity information;
• perform, using the link parity information, an error correction operation on the data and the inversion configuration;
• and
• invert, based on the inversion configuration, one or more portions of the data to generate second data.

A system, comprising:

• a host system;
• a memory apparatus;
• a host interface between the host system and the memory apparatus;
• and
• one or more controllers configured to:
• invert, by the host system and based on an inversion configuration, one or more portions of first data to generate second data;
• generate, by the host system, link parity information associated with the second data and the inversion configuration;
• communicate, from the host system to the memory apparatus and via a first bus of the host interface, a message comprising the second data, the inversion configuration, and the link parity information from the host system to the memory apparatus;
• and
• store the second data to one or more memory arrays of the memory apparatus.