US 2026/0080138 A1 · System for Correction of Circuit Verification Code

Abstract

A system generates verification code for a circuit design, such as a circuit design specified in RTL. An RTL file and specification are parsed to obtain ports, design parameters, and other functionality of the circuit design. The parsed RTL file and specification are processed by an LLM to generate a model including descriptions of the ports, design parameters, basic functionality, end-to-end functionality, corner-case scenarios and error scenarios. The model is processed by an LLM to generate a test plan that is processed by an LLM to generate verification code, such as simulation unit tests or formal verification assertions. The verification code may be revised by an LLM to correct syntax errors, improve performance, generate helper assertions, or generate auxiliary logic.

Claims20

Dependent claims

A method generating training data comprising:

receiving, by a computer system, a plurality of error codes for an electronic design automation (EDA) tool;
generating a plurality of training data entries by, for each training data entry:
prompting a first large language model (LLM) to modify functional code to generate error-producing code that will result in an error code of the plurality of error codes when processed by the EDA tool;
using the error-producing code as an input of the each training data entry;
and
using the functional code as a desired output of the each training data entry;
and
training, by the computer system, a second LLM to correct errors, with the plurality of training data entries.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/890,484Filed 19 Sep 2024

Published

19 Mar 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 30/3308
Design verification, e.g. functional simulation or model checking: using simulation
G06F 30/31
Circuit design: design entry, e.g. editors specifically adapted for circuit design
G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking
G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking

System for Correction of Circuit Verification Code

Life of this patent

System for Correction of Circuit Verification Code

Life of this patent

Abstract

Claims20