Scalable partitioning of functions within application specific integrated circuit or microelectronics device

A semiconductor wafer comprising:

• a plurality of processing cores;
• and
• a plurality of die structures each comprising at least one processing core of the plurality of processing cores,
• wherein each processing core comprises:
• a set of first input output (I/O) interfaces configured for communication between the processing core and at least one second processing core of the plurality of processing cores, wherein the processing core and the at least one second processing core are comprised in a first die structure of the plurality of die structures;
• and
• a second input output (I/O) interface configured for communication between the processing core and at least one third processing core of the plurality of processing cores, wherein the at least one third processing core is comprised in a second die structure of the plurality of die structures,
• wherein the plurality of processing cores are spaced apart by a target distance associated with separating one or more processing cores of the plurality of processing cores or one or more die structures of the plurality of die structures from the semiconductor wafer.