Communication protocol using free-space connectivity

A device comprising:

• a first die and a second die, the first die comprising a data transmission interface configured to transmit and receive signals and a processor configured to:
• generate a transmission asynchronous pattern;
• receive a response pattern via the data transmission interface indicating whether the transmission asynchronous pattern was received by a second die;
• and
• control a data transfer between the first die and the second die via the data transmission interface based on the response pattern, the second die comprising:
• a data transmission interface configured to transmit and receive signals and a processor configured to:
• receive the transmission asynchronous pattern;
• check whether the received transmission asynchronous pattern is correct;
• generate a response pattern indicating whether the received transmission asynchronous pattern is correct;
• and
• control a data transfer between the first die and the second die via the data transmission interface based on the check whether the received transmission asynchronous pattern is correct.

A device comprising:

• a first die and a second die, the first die comprising:
• an encoder comprising a plurality of encoder outputs and configured to generate bit signals on the encoder outputs of the plurality of encoder outputs;
• a plurality of transmit analog front end circuits configured to transmit signals, each transmit analog front end circuit coupled to an encoder output of the plurality of encoder outputs, wherein the encoder is configured to:
• in a first time period provided for first bit signals, provide a first bit signal of a first bit signal level representing a first bit value or a first bit signal of a second bit signal level representing a second bit value only on some encoder outputs of the plurality of encoder outputs;
• and
• in a second time period provided for second bit signals, the second time period immediately following the first time period, provide a second bit signal of a first bit signal level representing a first bit value or a second bit signal of a second bit signal level representing a second bit value only on some encoder outputs of the plurality of encoder outputs in which no first bit signals have been provided in the first time period,
• wherein the second die comprises:
• a plurality of receive analog front end circuits configured to receive signals, each receive analog front end circuit inductively coupled with an associated transmit analog front end circuit of the first die;
• and
• a decoder comprising a plurality of decoder inputs and a plurality of decoder outputs, wherein each decoder input is coupled to an associated receive analog front end circuit of the plurality of receive analog front end circuits, wherein the decoder is configured to generate bit signals on the decoder outputs based on the signals received on the decoder inputs.