Stacked semiconductor die architecture with redistribution layers on dies stacked orthogonal to a base die or substrate

A microelectronic assembly, comprising:

• a die stack including:
• a first die having a first face and a second face opposite the first face, and a bottom edge extending between the first face and the second face of the first die,
• a redistribution layer on the first face of the first die,
• a second die having a first face and a second face opposite the first face, the second face of the second die parallel to the first face of the first die, and
• a spacer layer between the first face of the first die and the second face of the second die;
• a base having a top face and a conductive contact, wherein the bottom edge of the first die is substantially parallel to the top face of the base, and the first face of the first die and the second face of the second die are substantially perpendicular to the top face of the base;
• and
• a solder coupled to the conductive contact and the redistribution layer.

A provides a process of making a semiconductor package substrate, the method comprising:

• providing a die stack including:
• a first die having a first face, a second face, and a bottom edge extending between the first face and the second face,
• a first conductive contact adjacent to the bottom edge of the first die,
• a redistribution layer on the first face of the first die, the redistribution layer coupled to the first conductive contact,
• a second die having a first face and a second face opposite the first face, the second face of the second die parallel to the first face of the first die, and
• positioning the die stack on a top face of a base, with the first face of the first die and the second face of the second die substantially perpendicular to the top face of the base;
• and
• coupling the first conductive contact with a base conductive contact on the base.