US 2026/0076207 A1 · SELECTIVE BACKSIDE ETCH FOR 3-D IC STACK

Abstract

Integrated circuit structures and fabrication methods that substantially prevent or mitigate damage that plasma etching may cause to the FETs of a top integrated circuit in a 3-D integrated circuit (IC) stack. Embodiments of such IC structures include (1) use of substrate contacts (S-contacts) within the top integrated circuit, ICT, of the 3-D IC stack connected to the gates of FETs that may be damaged by plasma etching, and (2) selective retention of the substrate/handle wafer of ICT aligned and in electrical contact with such S-contacts so as to conduct plasma charge away from the gate oxide of the protected FETs. In addition, the novel integrated circuit structures provide an additional benefit by providing thermal dissipation paths (heat sinks) for the 3-D IC stack.

Claims20

Dependent claims

A three-dimensional integrated circuit (IC) stack, including:

(a) a first IC including a bonding face;
and
(b) a second IC including:
(1) a bonding face;
(2) at least one substrate contact electrically coupled to a corresponding gate of a field-effect transistor (FET) within the second IC;
and
(3) at least one patterned post-etching handle remnant aligned and in electrical contact with a corresponding one of the at least one substrate contact;
wherein the bonding face of the second IC is bonded to the bonding face of the first IC.

5 more elements

Dependencies are inferred from the claim text.

Selective backside etch for 3-d ic stack

Life of this patent

Selective backside etch for 3-d ic stack

Life of this patent

Abstract

Claims20