Semiconductor structure and integrated assembly

A semiconductor structure, comprising:

• a first surface and a second surface that are opposite to each other;
• a first connection pad and a second connection pad, disposed on the first surface;
• a third connection pad, a fourth connection pad, and a fifth connection pad, disposed on the second surface;
• and
• a memory cell region, wherein the memory cell region is disposed between the first surface and the second surface, and comprises a first memory cell array and a second memory cell array that are arranged at an interval, the first memory cell array comprises a plurality of first semiconductor devices arranged in a first direction, and the second memory cell array comprises a plurality of second semiconductor devices arranged in the first direction;
• wherein
• the first connection pad and the fourth connection pad are connected to the first semiconductor device, the second connection pad and the fifth connection pad are connected to the second semiconductor device, the memory cell region further comprises a first connection portion, the first connection portion is connected to at least one of the first semiconductor device and the second semiconductor device, and the third connection pad is connected to the first connection portion.

An integrated assembly, comprising:

• a first semiconductor structure, wherein the first semiconductor structure comprises a first surface, a first connection pad and a second connection pad are disposed on the first surface, the first semiconductor structure further comprises a memory cell region, the memory cell region is disposed below the first surface, the memory cell region comprises a first semiconductor device and a second semiconductor device, the first connection pad is connected to the first semiconductor device, the second connection pad is connected to the second semiconductor device, and a first connection portion is disposed between the first semiconductor device and the second semiconductor device;
• and
• a second semiconductor structure, wherein the second semiconductor structure has a first bonding surface in bonding connection with the first surface of the first semiconductor structure, the second semiconductor structure comprises a third semiconductor device and a fourth semiconductor device, the third semiconductor device and the first semiconductor device are connected to the first connection pad by using the first bonding surface, the fourth semiconductor device and the second semiconductor device are connected to the second connection pad by using the first bonding surface, the second semiconductor structure further has a common connection portion, and the common connection portion is at least connected to the third semiconductor device or the fourth semiconductor device;
• wherein
• the first semiconductor structure further comprises a second surface, a third connection pad, a fourth connection pad, a fifth connection pad, and a sixth connection pad are disposed on the second surface, the third connection pad is connected to the first connection portion, the fourth connection pad is connected to the first connection pad, the fifth connection pad is connected to the second connection pad, and the sixth connection pad is connected to the common connection portion.